The Selective Read-out Processor for the CMS Electromagnetic Calorimeter

1. The Selective Read-out Processor for the CMS Electromagnetic Calorimeter Irakli Mandjavidze DAPNIA, CEA Saclay,91191 Gif-sur-Yvette, France Irakli.MANDJAVIDZE@cea.fr

2. Overview • Motivation and Goals • The CMS ECAL read-out system and SRP • SRP Challenges • SRP Design • Platform FPGAs • Xilinx Virtex-II Pro devices • Firmware • Optical communication channels • Current Status • Conclusive remarks Irakli.MANDJAVIDZE@cea.fr

3. Motivation and goals • CMS DAQ capabilities • Total event size: 1 Mbyte • Allowed average ECAL event size: 100 Kbyte • Data throughput of 100 Gbyte/s • ECAL raw data • Size: 1.5 Mbyte • Bandwidth: 150 Gbyte/s @ 100 kHz L1 trigger rate • Reduction factor of almost 20 is necessary • Crystal zero suppression: non-linearity and degraded energy resolution • Selective Read-Out • Define zones of interest on event-by-event basis • Read full precision data from channels within these zones • Apply strong zero suppression on the rest of channels Irakli.MANDJAVIDZE@cea.fr

4. The ECAL Read-out System Raw data1.5 Mbyte Selectiveread-out flags ECAL 40 MHz Front-end electronics Trigger Triggertowerflags L1 Accept 100 kHz Read-out Selective read-outprocessor: SRP Selected data 5 µs timing budget 100 Kbyte High level triggers and DAQ Asynchronous hard real-time system Irakli.MANDJAVIDZE@cea.fr

5. Type of Selective Read-out Algorithms N N N N N N N N N N ET N N C N N High N N N N N Low N N N N N Suppressed Single Center Neighbors 120 High threshold 2 GeV 100 ZS (0σ) 80 Event size (KB) ZS (1σ) 60 ZS (2σ) 40 0.5 0.6 0.7 0.8 0.9 1.0 Low threshold (GeV) • Sliding windows algorithm • Trigger towers (TT) are classified as • Singles, centers, neighbors: full precision read-out • Suppressed: zero suppression read-out • Complemented by coarse grain data • i.e. energy deposited in all TTs Reduction factor of 20 • detector performance: no noticeable degradation Irakli.MANDJAVIDZE@cea.fr

6. SRP Challenges • Asynchronous operation at 100 kHz L1 trigger rate • 5 µs timing budget • High number of input / output channels • ~200 optical communication links • 1.6 Gbit/s throughput per link • Certain flexibility to allow changes and evolution of selective read-out algorithms Combine advances in technologies of • the programmable logic (FPGA) • the optical communication Irakli.MANDJAVIDZE@cea.fr

7. SRP Architecture • Compact system: single VME 6U crate • 12 identical VME64x compliant boards • 3 boards covering each of 4 ECAL partitions • Note: the SRP board is used also as SRP tester • VME-PCI interface board with a contol PC • Boindary Scan controller for remote firmware management Just one custom board to develop and maintain End-cap- Halfbarrels - + End-cap+ BoundaryScanController VME-PCIinterface Irakli.MANDJAVIDZE@cea.fr

8. SRP Boards P1 P2 FPGA XilinxVirtex-II Proxc2vp70-6-ff1704 VME buffers Power supply Contrôleur JTAG VMESerial linksAlgorithmsTrigger IF FPROMs Clocksynthesizer TTFRx SRFTx SRPRx SRPTx Trigger Interface Parallel optics Trigger, timing, and control Aux.connector Throttling TTSOut Cons., JTAG O/E • VME64x compliant board with PnP capability • 3 firmware: « barrel », « end-cap », « tester » • sharing a bulk of VHDL code Irakli.MANDJAVIDZE@cea.fr

9. SRP Boards • 12 layers, 1.6mm thick • Up to 20 bidirectional optical communication links at 1.6 Gbit/s each • 40 differential pairs with 100Ω controlled impedance • Synthesizable clock • Monster FPGA with 1704-pin ball grid array package Reload StratusLEDs JTAG Triggerthrottle SRP TTF SRF RS232 Trigger Reset Irakli.MANDJAVIDZE@cea.fr

10. Xilinx 2vp70 Virtex-II Pro 2 PowerPC 405 CPUs @ 300 MHz 20 RocketIO transceivers up to 3 Gbit/s 18 kbit dual-port memories Flexible reconfigurable System-On-Chip Devices Programmable logic cells combinatorial and synchronous Versatile IOs Single ended and differential Hard IP cores Clock management Memory blocks Serial transceivers Embedded processor(s) Plus various soft IP cores Microcontrollers, network IF... Platform FPGAs DCM MGT MEMORY CPU Irakli.MANDJAVIDZE@cea.fr

11. Firmware Firmware organization 40 MHz 40 MHz VME PowerPC80 MHz RS232 console SRP board 80 MHz pipeline logic Peripheral bus Memory128 KB Processor bus Optical IO Slave interface Bridge 32-bit R/W • System-on-Chip design: handy for debugging and monitoring • embedded 80 MHz PowerPC with 128 Kbyte memory • stand-alone “C” applications for testing, debugging and monitoring • 32-bit slave interface on a 40 MHz peripheral bus • SRP Barrel and Endcap: 6 000 000 equivalent logic cells: 40% • 3.5 µs latency from L1 accept till SR flags delivered to the read-out • SRP Tester: 8 000 000 equivalent logic cells: 60% Plenty of resources for future enhancements Irakli.MANDJAVIDZE@cea.fr

12. Optical communication channels • Trigger-SRP and SRP-Read-out links Fan-in/Fan-outmodules Individual LC fibers 12-fiber MTP cables SRP Trigger Up to 12deserializersin FPGA Rx Serializer Tx Up to 12serializersin FPGA Readout Tx Deserializer Rx Small form factorpluggabletransceivers Pluggableparallel opticmodules Irakli.MANDJAVIDZE@cea.fr

13. Optical communication channels Passive optical cross-connect SRP2 Up to 8deserializersin FPGA Rx SRP3 Up to 8serializersin FPGA Tx Pluggableparallel opticmodules • SRP-SRP links • are needed to exchange information on frontiers • passive optical cross-connect: all-to-all connectivity Irakli.MANDJAVIDZE@cea.fr

14. Optical communication channels Tx • Measurements done with the LeCroy Serial Data Analyzer Paralleltransmitter MPO/MPOcable 2m LC/LCcable 30 m FDM Serial DataAnalyzer • ~0.8 UI eye opening • 0.65 is required for 10-12 BER by specifications 0.8 UI @ 10-12 BER Irakli.MANDJAVIDZE@cea.fr

15. Some Photos • Test system with prototypes • one card tests another VME crate with thetwo prototypes Control PC & Consolefor theembeddedSoC Processor LeCroySerialDataAnalyzer Irakli.MANDJAVIDZE@cea.fr

16. Some Photos • Test system with all 12 SRP boards • organized as 6 barrel and 6 tester boards Passive opticalcross-connect VME crate with12 boards Irakli.MANDJAVIDZE@cea.fr

17. Some Photos • Barrel SRP boards installed in the CMS service cavern Fan-in/Fan-out modulesandindividual LC fibers Cross-connect & 12-fiber MPO cables 6 barrel SRP boards Patch-panel & 12-fiber MPO cables Irakli.MANDJAVIDZE@cea.fr

18. Summary • All SRP boards produced and verified • 12 + 4 spares + 2 completely operational prototypes • up to 100 kHz trigger rate • weeks of operation without communication link errors • 6 barrel boards installed at CERN • commissioning underway • 6 end-cap boards to be commissioned early in 2008 • together with trigger and read-out electronics • 6 spare boards as development systems • 4 at CERN and 2 at Saclay Impatient to meet the very first collisions Irakli.MANDJAVIDZE@cea.fr

19. Just a little drop in the Sea(MS)... Only one crate 12 electronic boards but extremely attractive Modern Platform FPGAs Multi gigabit per second links Parallel optics System-on-chip design Les mots de la fin... An insight of electronics to be used in HEP experiments at future colliders Irakli.MANDJAVIDZE@cea.fr