IO and Constraints (IO discussion from Chapter 9)

1. IO and Constraints(IO discussion from Chapter 9)

2. Agenda • SelectIO • SSTL • HSTL • PCI • LVDS • Digitally Controlled Impedance (DCI) • Constraints • Pin sites • Voltage bank standard • Block location • Time • tPD • Period • Offset

4. E EM VII VII-Pr S3 V4 V

5. E EM VII VII-Pr S3 V4

6. V E EM VII VII-Pr S3 V4

7. V E EM VII VII-Pr S3 V4

8. V E EM VII VII-Pr S3 V4

9. SSTL3-II Stub Series Terminated Logic

10. SSTL2-I

11. HSTL Class I High Speed Transceiver Logic

12. Basic LVDS Low Voltage Differential Signaling

13. Spice Simulations of LVDS

14. Multi Drop LVDS

15. 20 Loads of Multi Drop LVDS

16. LVDS Inter Chip Link

17. Basic Bus LVDS

18. 20 Load Multi Point BUS LVDS

19. PCI Switching Waveforms Peripheral Component Interconnect

20. Virtex “brute force” I/O JTAG

21. DDR I/O Flip Flops

22. Multiplexed “Slave” Latch

23. Digitally Controlled Impedance

24. DCI “Transistor Tree”

25. N-Channel Impedance Tuning

26. P-Channel Impedance Tuning

27. DCI Impedance Matching Strategy

28. SSTL2 with and without DCI

29. Constraints

30. Constraints • Xilinx constraint guide ~250 pages long • ~2/3 are on specific Xilinx constraints • Lots of variety • Tangibility can be a problem…. • Pinout constraints are obvious (pin diag) • Location constraints are obvious (FPGA Editor) • Timing is only obvious by examining the reports ….in detail • A big difference is simply whether you are inside or outside the FPGA • Common tool: unified constraint file “ucf”

31. # clock pin for Nexys 2 Board NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0 # RS232 connector NET "Rx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX NET "Tx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX NET "alarm" LOC = "J14"; # Period constraint for 50MHz operation NET "clk" PERIOD = 20 ns HIGH 50%; #More elaborate timespecs (stolen from the PicoBlaze design) TIMESPEC TS01 = FROM : FFS : TO : FFS : 20 ns; TIMESPEC TS02 = FROM : RAMS : TO : FFS : 20 ns; TIMESPEC TS03 = FROM : FFS : TO : RAMS : 20 ns; TIMESPEC TS04 = FROM : RAMS : TO : RAMS : 20 ns; TIMESPEC TS05 = FROM : FFS : TO : PADS : 20 ns; TIMESPEC TS06 = FROM : PADS : TO : FFS : 20 ns; TIMESPEC TS07 = FROM : PADS : TO : RAMS : 20 ns; #parking BRAM at another site (should move it to lower right) INST program_rom/ram_1024_x_18 LOC = RAMB16_X1Y0;

32. UCF Comment • The constraints manual has lots of little details that need to be read through • One that had me pulling my hair out was the location constraint with a hierarchical design • Note the bottom constraint on previous slide is done “hierarchically” with high level instance \ lower level instance The error message for this was cryptic!

33. Pin Constraints • Pin constraints are the most tangible • However, they should be used sparingly • Early pin constraints permit early PCB mfg • Design S/W strips out designated pins not used by the design automatically • If you plug NEXYS2 ucf into the “uart_clk” design, all but four pins should drop out and a bunch of warnings appear to tell you • If you want to reserve pins for future use, you need to insert dummy circuitry

34. A Location Constraint Location Address Nexys2 Board

35. Free Route .. No constraints UCF included but all commented out Natural clustering to get proximity For speed as a default Black columns on right and left are Where BRAMS and interconnect are Parked Note: the design used for these examples is the PicoBlaze soft processor

36. Added clock, rx, tx and alarm UCF included uncommented 4 pins to Land on NEXYS2 pins for clock, rx, tx And LED1 Design remains fairly clustered in upper right corner naturally by S/W

37. Added Period Constraint UCF addition to previous slide, uncommented the period constraint to get 50 MHz Design tends to “smear” down still on The right hand side of the die, but less dense function placement

38. Added TS1-7 Uncommented the seven TS specs in addition to the pin and period constraints from previous slides. Shouldn’t be that different from just the period constraint, and comparison shows that it is very close if not identical

39. Park BRAM @ lower left BIG CHANGE HERE Added a location constraint to park the BRAM at the lower left side of the Die: X0Y0 Pinouts stayed, but logic pretty much has to track the BRAM to meet the timing requirements, so wholesale reallocation occurs

40. Park BRAM @ Lower Right Another BIG CHANGE Moved the BRAM from lower left to lower right, while keeping pins where they were as well as period and timing constraints Naturally BRAMS drag along the PicoBlaze, UART and other support logic to maintain the timing This is what experimenting is all about – try things and see what happens

41. Period Constraints(Life inside the fabric)

43. Related Periods

44. Unrelated Clock Domains(Can be different frequencies and/or different phases of same freq)

45. DCM can offer some help …

46. Period Constraint Associatedto Clock in pin of the DCM gets “transformed” Phase is a keyword

47. Table 1 continued

48. Gated Clocks Period constraint on “Clock” doesn’t carry thru to Clk_Div

49. What’s covered by Period Constraints? Note: IO Pads are not included – covered with Offset Constraints

50. Priorities Range:+/- 255 Lowest number = highest priority