1 / 8

DATA(31:0) – output DATA DATA(32) – output BeginOfEvent DATA(33) – output EndOfEvent

DATA(31:0) – output DATA DATA(32) – output BeginOfEvent DATA(33) – output EndOfEvent EFempty – output. Optional ReadData – input TEST – output. Optional EvReady – output. ExtClk – input, the same as for PXD side. CHANGED!!!. DATAtoPXD(31:0) – output DATA

gisela
Download Presentation

DATA(31:0) – output DATA DATA(32) – output BeginOfEvent DATA(33) – output EndOfEvent

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. DATA(31:0) – output DATA DATA(32) – output BeginOfEvent DATA(33) – output EndOfEvent EFempty – output. Optional ReadData – input TEST – output. Optional EvReady – output. ExtClk – input, the same as for PXD side CHANGED!!!

  2. DATAtoPXD(31:0) – output DATA DATAtoPXD(32) – output BeginOfEvent DATAtoPXD(33) – output EndOfEvent EMPTYtoPXD – output RDENfromPXD – input ExtClk – input, the same as for B2Link side FULLtoPXD – output, asynchronous with ExtClk. May be used, may be not.

  3. Registers access by B2Link 1. Signals from B2Link synchronous with Clk32MHz clock WRITE Clk32MHz aBLA(6:0) LRW aINLD(7:0) CSB READ aBLA(6:0) OULD(7:0) 2. Signals from B2Link asynchronous with Clk32MHz clock I have to prepare the timing information

  4. TTAck is driven by BUSY signal TTTrg may be chosen as the TRYG signal (see XLSsh1, CFR register). TTRSV has no source

  5. X1Y0 GTP (U17) for B2Link

  6. X0Y0 GTP (U18) for PXD

  7. X1Y0 GTP (U16) for B2Link

  8. Clocks and GlobalReset Clocks: 1. Clk32MHz – clock from on board oscillator. Always ON. 2. Clk – general clock in design (look at XLSsh1, CFR register). One may choose from: DCLK – clock from FADC [CFR(1) = 0] Clk32MHz - clock from on board oscillator [CFR(1) = 1 and CFR(0) = 0] TT32Clk – clock from TTD divided by 4 [CFR(1) = 1 and CFR(0) = 1] GlobalReset: There are three sources: InRes – generated inside firmware after firmware is loaded (reset on start) ButRes – on board button RESET SoftRes – SoftwareReset (look at XLSsh1, M0R(0) register).

More Related