Assignments documentation dr fearghal morgan
This presentation is the property of its rightful owner.
Sponsored Links
1 / 3

Assignments Documentation Dr Fearghal Morgan PowerPoint PPT Presentation


  • 49 Views
  • Uploaded on
  • Presentation posted in: General

Assignments Documentation Dr Fearghal Morgan. Aim : Capture and implement a digital i mage p rocessing s ystem implemented on the Digilent Xilinx Spartan-3 FPGA development system, controlled by & communicating with host GUI appliedVHDL project overview The project incorporates

Download Presentation

Assignments Documentation Dr Fearghal Morgan

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Assignments documentation dr fearghal morgan

Assignments DocumentationDr Fearghal Morgan

  • Aim :

  • Capture and implement a digital image processing system implemented on the Digilent Xilinx Spartan-3 FPGA development system, controlled by & communicating with host GUI

  • appliedVHDL project overview

  • The project incorporates

    • Digital systems analysis and design

    • Use of a structured design, documentation, test and implementation methodology

    • VHDL design entry

    • VHDL testbench and simulation

    • VHDL Bus Functional Model (BFM) creation

    • VHDL Synthesis

    • FPGA Implementation and hardware test

  • The following resources are provided:

    • Template Xilinx ISE project files, template VHDL files, Modelsim macro files

    • Host serial interface GUI

    • Digilent Spartan-3 FPGA Hardware Development Module

    • Xilinx ISE and Modelsim XE EDA tools


Assignment steps

Assignment steps

Several exercises form part of the larger appliedVHDL project, as follows:

Follow assignment instructions to complete each element in sequenceSubmission instructions

Project PhasesPhase 1 : displayCtrlr Multiplexed 7-seg display & LED ctrlr

Phase 2 : cascadedBCDCntr&displayCtrlr: Cascaded BCD counter connected to displayCtrlr

Phase 3 :appliedVHDLV1CSR r/w, display controller, serial I/O

Phase 4 :appliedVHDLCSR r/w, display controller, serial I/O,SRAM r/w controller, SRAM Bus Functional Model (BFM), Datapath controller, DSP function (image processing fn)


Appliedvhdl system design documentation

appliedVHDL System Design Documentation

  • Structured Design and Documentation methodology is used to describe the appliedVHDL project. (Link to overview presentation)

  • Structured design documentation set elements:

    • Top level Context Diagram (CD)

    • Process Descriptions

    • Data Dictionaries (DD)

    • Data Flow Diagrams (DFDs)

    • Functional Partitions (at unit and top levels)

    • Timing Diagrams

    • Flow charts (Finite State Machine (FSM) descriptions)

  • Note : alternative design solutions exist to that provided. Adhere to the appliedVHDL design architecture provided though suggest alternatives as the course progresses.


  • Login