JEITA – DASC Joint Meeting

1. JEITA – DASC Joint Meeting January 29, 2010 Yokohama, Japan

2. DASC Overview Stan Krolikoski July 1, 2010 Shin-Yokohama, Japan

3. Agenda • Call to Order • Introductions • DASC activities update by Stan • JEITA standardization activities update by Kojima-san • AOB

4. DASC Officers • Stan Krolikoski, Cadence, Chair • Karen Bartleson, Synopsys, Vice Chair • Kathy Werner, Freescale, Secretary • Victor Berman, self, Treasurer

5. DASC Standards Issued in 2010 • 1497-2001 (SDF) • 1850 (PSL)

6. IEEE P1076.1 VHDL-AMS WG • Charter: Revise, maintain and enhance • IEEE Std 1076.1: IEEE Standard VHDL Analog and Mixed-Signal Extensions • Adds support for continuous time and mixed-signal modeling to VHDL • First approved in 1999 • Maintenance revision approved in 2007 • IEEE Std 1076.1.1: IEEE Standard VHDL Analog and Mixed-Signal Extensions—Packages for Multiple Energy Domain Support • Definitions for electrical, thermal, mechanical, etc. energy domains • First approved in 2004 • Working Group activities in 2010 • Complete revision of IEEE Std 1076.1.1 • Maintenance revision, no new features • IEEE balloting group formed, ballot to start in July • Revision of IEEE Std 1076.1 • Incorporate IEEE Std 1076-2008 changes into IEEE Std 1076.1 • Enhance language by adding selected new features • Ran user survey and call for participation. Responses used to prioritize projects • Preliminary planning complete, PAR under development • Work on projects identified to be included in the revision has started • Schedule depends on number of participants • Contacts: • Web site: http://www.eda.org/vhdl-ams • WG Chair: Ernst Christen, christen.1858@verizon.net

7. IEEE1647 e WG • . • e Functional verification language standard • Currently working towards a 2010 update to the standard • Reviewing final issues, aiming for final version of LRM for WG review. • Aiming to complete review process by mid-year. • Chair contact: Darren Galpin (Darren.Galpin@infineon.com) • Group e-mail: ieee1647@eda.org

8. IEEE P1666 SystemC WG • Charter is to update the 1666-2005 standard and to add TLM 2.0 to SystemC standard • Work is moving very nicely ahead • Numerous errata from 1666-2005 have been fixed • Roughly ½ of the clarification and new features have been made • Enhancements already agreed • TLM-1 Message Passing Interface • Process control extensions • Multiple other lesser enhancements “in process” • Expectation to go to ballot by end of year • Chair: Stan Krolikoski (stanleyk@cadence.com)

9. IEEE 1685 IP-XACT WG • Group charter • Standardize the IP-XACT work done by The SPIRIT Consortium through the IEEE process • 2009 milestones • Documents prepared for ballot (July) – held and passed • Initial ballot passed with comments (August) • Comments address and recirculation ballot passed (September) • Package submitted to RevCom and added to December’s agenda for approval (October) • RevCom approved (December) • 2010 Accomplisments • Standard published (February) • Accellera provided for no-cost individual downloads: • http://standards.ieee.org/getieee/1685/index.html • Work group’s activities are complete, currently no further work planned • Contacts • Chairman – Greg.Ehmann@VirageLogic.com • Secretary – Gary.Delp@gmail.com

10. P1699 – Rosetta WG • Rosetta: The goal of Rosetta project is to provide language support for true system-level design. The Rosetta view of system level design is centers on the need to bring together information from multiple domains to predict the system-level impacts of local design decisions. In support of this, Rosetta provides mechanisms for defining system-level functional requirements and constraints, defining heterogeneous specifications and specification domains, and composing specifications to define complete systems. Individual specifications are written using semantics and vocabulary appropriate for their domains and composed to define systems. Information from multiple specification domains is composed by defining interactions between them. • Charter: • Develop a standard for the Rosetta System-Level Specification Language • Develop a collection of Rosetta Base Domains for System-Level Specification • Broaden the use of System-Level Specification in Electronics Design • 2009 Milestones and Activities: • Developed a semantics for Transaction Level Specification for state-based systems • Developed a semantics for inter-facet synchronization and sequencing • Developed initial syntax and semantics for interactions • Processed over 500 issues in the standard development database • Established an LRM Working Group to manage updates to the standard document • Delivered tutorials at ASE and FDL • 2010 Plans and Tasks: • Update draft LRM to reflect additions and changes from 2009 • Release the first full draft LRM for discussion in the full Working Group • Finalize semantics for facets and interactions • For more information: • Dr. Perry Alexander, Chair – alex@ittc.ku.edu / +1.785.864.7741 • Rosetta Web Page – http://www.rosetta-lang.org • System-Level Design with Rosetta, Morgan Kaufmann Publishers • LRM Working Group meets weekly on Friday afternoons

11. P1734 – Quality IP WG Charter • Provide unified quality measurement views • Facilitate IP use and integration • Facilitate IP improvements • Based on VSIA QIP using XML • Allows platform portability • Facilitates user specific extensions 2009 Accomplishments • Completed schema development • Developed database for QIP information • “Golden” XML extracted from db • Completed XML validated against schema • Example application developed • Validates XML and schema • Validates use cases 2010 Plans • Complete documentation • Release for ballot • Re-invigorate participation • Several new participating companies and entities engaged • Currently finalizing testing Chair • kathy.werner@freescale.com

12. P1735 - Recommended Practice for Encryption and [Use Rights] Management of Electronic Design Intellectual Property (IP) • Chartered to reconcile the IP Encryption and Design Protection technologies across the family of DASC sponsored standards through a "Recommended Practices" document, targeted at three communities: • IP producers looking for best practices guidance • EDA tool providers/users looking for inter-operability • Working Groups looking for subject matter experts • In 2009 the working group resolved inter-operability issues in IEEE Std1800 and IEEE Std1076. • In 2010, the working group is addressing: • License management improvements • Key Management • Rights Management extensions • LRM specification improvements • Contact: • Steven J. Dovich dovich@cadence.com (P1735 chair)

13. P1800- SystemVerilog WG • Charter: To maintain and extend SystemVerilog as a Hardware Design and Verification Language • PAR for next revision of the standard has been approved • Technical work is planned to complete in October 2011 • Ballot is planned for March of 201 • Scope document is under development • For further information contact • ieee1800@eda.org

14. P1801- Design and Verification ofLow Power Integrated Circuits • Scope: • The specification of a format to be used in defining the low power design intent for electronic systems and electronic intellectual property. The format provides the ability to specify the supply network, switches, isolation, retention and other aspects relevant to power management of an electronic system. The standard defines the relationship between the low power design specification and the logic design specification captured via other formats (e.g., standard hardware description languages). • The standard provides portability of low power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification and implementation flow. • Activities • At the end of 2008 the working group finished the final draft, which was balloted and approved in January of 2009. It was released as an IEEE Standard 1801-2009 in March. (http://ieeexplore.ieee.org/servlet/opac?punumber=4809843) • The working group resumed meeting with the goal of providing answers to frequently asked questions, interpretations based on the “Sense of the Workgroup” (to be posted at http://www.accellera.org/activities/p1801_upf), and to form the scope of the next version • Next version: • After collecting *much* user feedback (see contact) • Currently projected: 2011-2012. • Contact: p1801-chair@lists.accellera.org (Gary Delp, Silver Loon Systems)

15. P1801- Design and Verification ofLow Power Integrated Circuits • Scope: • The specification of a format to be used in defining the low power design intent for electronic systems and electronic intellectual property. The format provides the ability to specify the supply network, switches, isolation, retention and other aspects relevant to power management of an electronic system. The standard defines the relationship between the low power design specification and the logic design specification captured via other formats (e.g., standard hardware description languages). • The standard provides portability of low power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification and implementation flow. • Activities • V2 approved January of 2009. It was released as an IEEE Standard 1801-2009 in March. (http://ieeexplore.ieee.org/servlet/opac?punumber=4809843) • The working group resumed meeting with the goal of providing answers to frequently asked questions, interpretations based on the “Sense of the Workgroup” (to be posted at http://www.accellera.org/activities/p1801_upf), and to form the scope of the next version • Next version: • After collecting *much* user feedback (see contact) • Currently projected: 2011-2012. • Contact: p1801-chair@lists.accellera.org (Gary Delp, Silver Loon Systems)

16. Backup

17. P1666 Officers • Stan Krolikoski (OSCI DR) Chair-elect • Jerome Cornet (ST DR) Vice Chair-elect • Dennis Brophy (Mentor DR) Secretary

18. P1666 Member Entities Accellera Cadence Freescale Intel JEITA Mentor NXP OSCI ST Micro STARC Synopsys TI