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Computer Architecture: A Constructive Approach Implementing SMIPS Arvind

Computer Architecture: A Constructive Approach Implementing SMIPS Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology. The SMIPS ISA. Processor State 32 32-bit GPRs, R0 always contains a 0 PC , the program counter some other special registers

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Computer Architecture: A Constructive Approach Implementing SMIPS Arvind

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  1. Computer Architecture: A Constructive Approach Implementing SMIPS Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology http://csg.csail.mit.edu/SNU

  2. The SMIPS ISA • Processor State • 32 32-bit GPRs, R0 always contains a 0 • PC, the program counter • some other special registers • Data types • 8-bit byte, 16-bit half word • 32-bit word for integers • Load/Store style instruction set • data addressing modes- immediate & indexed • branch addressing modes- PC relative & register indirect • Byte addressable memory- big endian mode • All instructions are 32 bits http://csg.csail.mit.edu/SNU

  3. Instruction Execution • Execution of an instruction involves • 1. Instruction fetch • 2. Decode • 3. Register fetch • 4. ALU operation • 5. Memory operation (optional) • 6. Write back • and the computation of the address of the • next instruction http://csg.csail.mit.edu/SNU

  4. Implementing an ISA • Instructions fetch • requires an Instruction memory, PC • Decode • requires understanding the instruction format • Register Fetch • requires interaction with a register file with a specific number of read/write ports • ALU • must have the ability to carry out the specified ops • Memory operations • requires a data memory • Write-back • requires interaction with the register file http://csg.csail.mit.edu/SNU

  5. 6 26 opcode target J-type Instruction formats 6 5 5 5 5 6 opcodersrt rd shamtfunc R-type • Only three formats but the fields are used differently by different types of instructions 6 5 5 16 opcodersrt immediate I-type http://csg.csail.mit.edu/SNU

  6. 6 5 5 16 addressing mode opcodersrt displacement (rs) + displacement 31 26 25 21 20 16 15 0 6 5 5 5 5 6 0 rsrt rd 0 func rd  (rs) func (rt) opcodersrt immediate rt (rs) op immediate Instruction formats cont • Computational Instructions • Load/Store Instructions rs is the base register rt is the destination of a Load or the source for a Store http://csg.csail.mit.edu/SNU

  7. 6 5 5 16 opcoders offset BEQZ, BNEZ 6 5 5 16 opcoders JR, JALR 6 26 opcode target J, JAL Control Instructions • Conditional (on GPR) PC-relative branch • target address = (offset in words)4 + (PC+4) • range: 128 KB range • Unconditional register-indirect jumps • Unconditional absolute jumps • target address = {PC<31:28>, target4} • range : 256 MB range jump-&-link stores PC+4 into the link register (R31) http://csg.csail.mit.edu/SNU

  8. A single-cycle implementation rf pc CPU • A single-cycle MIPS implementation requires: • A register file with 2 read ports and a write port • An instruction memory , separate from data memory so that we can fetch an instruction as well as perform a data operation (Load/store) on the memory fetch & execute iMem dMem http://csg.csail.mit.edu/SNU

  9. but first a digression on types … http://csg.csail.mit.edu/SNU

  10. What is the type of this + ? Example: Complex Addition typedef struct{ Int#(t) r; Int#(t) i; } Complex#(numeric type t) deriving (Eq,Bits); function Complex#(t) \+ (Complex#(t) x, Complex#(t) y); Int#(t) real = x.r + y.r; Int#(t) imag = x.i + y.i; return(Complex{r:real, i:imag}); endfunction http://csg.csail.mit.edu/SNU

  11. Example: A 4-Instruction ISA typedefenum {R0;R1;R2;…;R31} RName; typedef union tagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName valueR; RName addrR;} Store } Instr deriving(Bits, Eq); typedef Bit#(32) Iaddress; typedef Bit#(32) Daddress; typedef Bit#(32) Value; http://csg.csail.mit.edu/SNU

  12. Deriving Bits typedefstruct { … } Foo deriving (Bits); • To store datatypes in register, fifo, etc. we need to know how to represent them as bits (pack) and interpret their bit representation (unpack) • Deriving annotation automatically generates the “pack” and “unpack” operations on the type (simple concatenation of bit representations of components) http://csg.csail.mit.edu/SNU

  13. 00 dst src1 src2 01 condR addrR 10 dst addrR 11 dst imm Tagged Unions: Bit Representation typedefuniontagged { struct {RName dst; RName src1; RName src2;} Add; struct {RName condR; RName addrR;} Bz; struct {RName dst; RName addrR;} Load; struct {RName dst; Immediate imm;} AddImm; } Instr deriving(Bits, Eq); Automatically derived representation; can be customized by the user written pack and unpack functions http://csg.csail.mit.edu/SNU

  14. Pattern-matching: A convenient way to extract datastructure components typedefuniontagged { void Invalid; t Valid; } Maybe#(type t); • The &&& is a conjunction, and allows pattern-variables to come into scope from left to right case (m) matches tagged Invalid : return 0; tagged Valid .x : return x; endcase x will get bound to the appropriate part of m if (m matches (Valid .x) &&& (x > 10)) http://csg.csail.mit.edu/SNU

  15. now back to SMIPS … http://csg.csail.mit.edu/SNU

  16. Single-Cycle SMIPS Register File PC Execute Decode +4 Data Memory Inst Memory Datapath is shown only for convenience; it will be derived automatically from the high-level textual description http://csg.csail.mit.edu/SNU

  17. Single-Cycle SMIPS code structure modulemkProc(Proc); Reg#(Addr) pc <- mkRegU; RFilerf<- mkRFile; Memory mem <- mkMemory; rulefetchExecute; //fetch letinstResp <- mem.iside(MemReq{…}); //decode letdecInst = decode(instResp); //execute letexecInst = exec(decInst, pc, rVal1, rVal2); if(instType Ld || St) … mem.dside(MemReq{…}); pc <= execInst.brTaken ? execInst.addr : pc + 4; //writeback if(instTypeAlu|| Ld) rf.wr(rDst,data); endruleendmodule; http://csg.csail.mit.edu/SNU

  18. Type: Instr(partial definition)Captures the fields for each instruction typedefunion tagged { struct{Rindxrbase; Rindxrdst; Simm offset;} LW;struct{Rindxrbase; Rindxrsrc; Simmoffset;} SW; struct{Rindxrsrc; Rindxrdst; Simmimm;} ADDIU;struct{Rindxrsrc; Rindxrdst; Shamtshamt;} SLL;struct{Rindxrsrc1; Rindx rsrc2; Rindxrdst; } ADDU;struct{Target target; } J;struct{Rindxrsrc; } JR;struct{Rindxrsrc; Rindxrdst; } JALR;struct{Rindxrsrc1; Rindx rsrc2; Simm offset;} BEQ;struct{Rindxrsrc; Simm offset; } BLEZ;void ILLEGAL;} Instrderiving(Eq); We need to define our own pack/unpack functions to match the MIPS instruction formats http://csg.csail.mit.edu/SNU

  19. Miscellaneous type defs typedef Bit#(5) Rindx;typedef Bit#(16) Simm;typedef Bit#(16) Zimm;typedef Bit#(5) Shamt;typedef Bit#(26) Target;typedefenum {Alu, Ld, St, Other} ITypederiving(Bits, Eq); typedefenum{Eq, Neq, Le, Lt, Ge, Gt, J, JR, N} BrTypederiving(Bits, Eq); typedefenum{Add, Sub, And, Or, Xor, Nor, Slt, Sltu, LShift, RShift, Sra} Funcderiving(Bits, Eq); http://csg.csail.mit.edu/SNU

  20. pack for type Instrpartial definition function Bit#(32) pack( Instrinstr );case( instr ) matchestaggedLW .it : return {opLW, it.rbase, it.rdst, it.offset};taggedSW .it : return {opSW, it.rbase, it.rsrc, it.offset};taggedADDIU .it : return {opADDIU, it.rsrc, it.rdst, it.imm}; taggedSLL .it : return {opFUNC, 5'b0, it.rsrc, it.rdst, it.shamt, fcSLL}; taggedJ .it : return {opJ, it.target}; taggedBEQ .it : return {opBEQ, it.rsrc1, it.rsrc2, it.offset}; endcaseendfunction Also need to define constants opLW, … http://csg.csail.mit.edu/SNU

  21. unpack for type Instrpartial definition functionInstr unpack( Bit#(32) instrBits );letopcode = instrBits[ 31 : 26 ];letrs = instrBits[ 25 : 21 ];letrt = instrBits[ 20 : 16 ];let rd = instrBits[ 15 : 11 ];letshamt = instrBits[ 10 : 6 ];letfunct = instrBits[ 5 : 0 ];letimm = instrBits[ 15 : 0 ];let target = instrBits[ 25 : 0 ];case ( opcode )opLW : return LW {rbase:rs, rdst:rt, offset:imm};… default : return ILLEGAL;endcaseendfunction http://csg.csail.mit.edu/SNU

  22. unpack for type Instrpartial definition case( opcode )opLW : returnLW {rbase:rs, rdst:rt, offset:imm}; opADDIU : return ADDIU {rsrc:rs, rdst:rt, imm:imm};opJ : return J {target:target };opJAL : return JAL {target:target};opFUNC: case ( funct )fcSLL: return SLL { rsrc:rt, rdst:rd, shamt:shamt };fcADDU: return ADDU { rsrc1:rs, rsrc2:rt, rdst:rd };fcJR: return JR { rsrc:rs};fcJALR: return JALR {rsrc:rs, rdst:rd};default : return ILLEGAL;endcasedefault : return ILLEGAL;endcase http://csg.csail.mit.edu/SNU

  23. Decoding Instructions: extracts fields needed for execution from each instruction decode 31:26 instType 31:26 aluFunc 5:0 inst 31:26 branchComp Pure combinational logic: will be derived automatically from the high-level description 20:16 rDst 15:11 25:21 rSrc1 20:16 rSrc2 15:0 imm ext 25:0 http://csg.csail.mit.edu/SNU

  24. Decoding Instructions functionDecodedInst decode(Bit#(32) inst, Addr pc); DecodedInstdInst = ?; letopcode = instrBits[ 31 : 26 ];letrs = instrBits[ 25 : 21 ];letrt = instrBits[ 20 : 16 ];let rd = instrBits[ 15 : 11 ];letshamt = instrBits[ 10 : 6 ];letfunct = instrBits[ 5 : 0 ];letimm = instrBits[ 15 : 0 ];let target = instrBits[ 25 : 0 ]; case (opcode) ... endcase returndInst; endfunction http://csg.csail.mit.edu/SNU

  25. Decoding Instructions:Load & Store case(opcode) LW, SW: begin dInst.instType = opcode==LW ? Ld : St; dInst.aluFunc = Add; dInst.rDst = rt dInst.rSrc1 = rs dInst.rSrc2 = rt dInst.imm = signExtned(imm); end … endcase http://csg.csail.mit.edu/SNU

  26. Decoding Instructions:R-Type ALU case(opcode) … RAlu: begin dInst.instType = Alu; dInst.aluFunc = case (funct) ... endcase; dInst.rDst = rd; dInst.rSrc1 = rs; dInst.rSrc2 = rt; end … endcase http://csg.csail.mit.edu/SNU

  27. Decoding Instructions:I-Type ALU case(opcode) … IAlu: begin dInst.instType = Alu; dInst.aluFunc = case (funct) ... endcase; dInst.rDst = rt; dInst.rSrc1 = rs; dInst.imm = opcode==SignedIAlu ? signExtend(imm): zeroExtend(imm); end … endcase http://csg.csail.mit.edu/SNU

  28. Decoding Instructions:Jump case(opcode) … J, JAL: begin dInst.instType = opcode==J ? J : Jal; dInst.rDst = 31; dInst.imm = zeroExtend({target, 2’b00}); end rJump: begin dInst.instType = funct==JR ? Jr : Jalr; dInst.rDst = rd; dInst.rSrc1 = rs; end …. endcase http://csg.csail.mit.edu/SNU

  29. Decoding Instructions:Branch case(opcode) … Branch: begin dInst.instType = Br; dInst.branchComp = case (opcode) ... endcase; dInst.rSrc1 = rs; dInst.rSrc2 = rt; dInst.imm = signExtend({imm, 2’b00}); end … endcase http://csg.csail.mit.edu/SNU

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