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MOSFETs. Metal Oxide Semiconductor Transistors ( MOSFETs ). Recommended Book: Sedra & Smith, Microelectronics, 4 th Edition Boylestad & Nashelsky, Electronic Devices …, 8 th Edition. Johns & Martin Analog Integrated Circuit Design. FET Notation. PMOS (N channel bulk). S. B. S.

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Mosfets
MOSFETs

  • Metal Oxide Semiconductor

  • Transistors

  • (MOSFETs)

Recommended Book:

Sedra & Smith,

Microelectronics, 4th Edition

Boylestad & Nashelsky,

Electronic Devices …, 8th Edition.

Johns & Martin

Analog Integrated Circuit Design

MOSFETs


Fet notation
FET Notation

  • PMOS (N channel bulk)

S

B

S

P

N

P

G

G

B

D

D

Arrow on

the Source

The FET is a

4 terminal device

  • NMOS (P channel bulk)

B

D

D

N

P

N

G

G

B

S

S

MOSFETs


Fet construction
FET Construction

W

L

  • In a MOSFET there are two important physical parameters,

  • W Width of the channel

  • L Length of the channel

MOSFETs


Fet operation
FET Operation

  • The FET is a

  • Voltage Control Current Source

  • The current that flows from the drain to the source is dependent on the voltage that is applied to the gate.

B

D

D

ID

N

P

N

G

G

S

S

MOSFETs


Fet operation1
FET Operation

  • MOSFETs come in two flavours,

  • enhancement and depletion

  • In Depletion MOSFETs the channel between the drain and the source already exists and changing the voltage on the gate reduces the channel. These are useful for very low voltage applications.

  • In Enchancement MOSFETs the channel between the drain and the source does not exist. Changing the voltage on the gate creates and expands the channel. These are the most common type used today and are the only type we’ll study in this course.

MOSFETs


Fet operation qualitative
FET Operation - Qualitative

VGS

NMOS

  • The current does not flow through any PN junction.

  • We place a positive voltage on the metal gate.

  • This attracts negative charge at the top of the bulk region near the gate.

  • If enough negative charge collects, then the P-type is converted to N type and then we have a path for current to flow from drain to source without ever leaving N-type.

  • The reverse happens for a PMOS.

GATE

Metal

IS

ID

N

N

P

Bulk

Source

Drain

MOSFETs


Fet operation qualitative1
FET Operation - Qualitative

VGS

NMOS

  • When no inversion region exists, then there are two PN junctions.

  • In normal operation, in an NMOS, the bulk must be lower than or of equal voltage to both the source and the drain or current simply flows from bulk to drain and source.

  • Assuming normal operation, with no inversion region, to get current from drain to source requires passing through two reverse biased PN junctions.

  • No current flows without an inversion region.

GATE

Metal

IS

ID

N

N

P

Bulk

Source

Drain

MOSFETs


Fet operation qualitative2
FET Operation - Qualitative

NMOS

  • There is NO dc current path between the metal and either the N or P type semiconductors.

  • An insulator SiO2 separates the metal from all other conducting substances.

  • In a MOSFET,

  • There is no current in or

  • out of the gate node.

GATE

Metal

Insulator

Semiconductor

MOSFETs


Fet operation quantitative
FET Operation - Quantitative

VGS

NMOS

  • There are only three equations of importance in this idealised MOSFET

GATE

Metal

IS

ID

N

N

P

Bulk

Source

Drain

MOSFETs


Fet operation quantitative1
FET Operation - Quantitative

  • VT is the minimum gate-source voltage required to obtain strong inversion in the bulk material.

  • VGS is the voltage difference between the gate and the source.

  • In an NMOS, VGS is positive. The source voltage is commonly ground.

  • In a PMOS, VGS is negative, the source voltage is commonly the positive supply voltage

MOSFETs


Fet operation quantitative2
FET Operation - Quantitative

  • The degree to which VGS exceeds VT is an important term in most of the expressions for the MOSFET. Commonly this value is given another name,

  • the overdrive voltage, VOD

  • the effective gate voltage, Veff

  • Thus for example, the current equation becomes

MOSFETs


Fet operation quantitative3
FET Operation - Quantitative

  • All field effect transistors suffer from a pinch-off effect.

  • This effect occurs because the width of the conducting channel is dependent on the gate-source voltage.

  • However current through the channel is resistive and causes a voltage drop between a point in the channel and the source.

  • Hence the effective voltage between the gate and the point in the channel is less than expected. It is this voltage that determines the width of the inversion region.

MOSFETs


Fet operation quantitative4
FET Operation - Quantitative

  • At some point the voltage dropped across the channel is so great that the effective voltage left to cause the inversion region is just sufficient to cause a strong inversion. This is the pinch-off voltage.

MOSFETs


Fet operation quantitative5
FET Operation - Quantitative

  • Pinch-off should be considered as a limit on the maximum current that can be passed by the MOSFET despite the driving voltage VDS

  • If more current was to flow then the channel would pinch-off further, potentially closing the link.

  • If less current was to flow then the channel would widen, allowing extra current to flow.

  • In practice, an equilibrium is reached and a maximum saturation current is obtained IDsat.

MOSFETs


Fet operation quantitative6
FET Operation - Quantitative

  • To see how this plays mathematically, for a given VGS, the gate-channel voltage must just equal VT, and now assume that pinch-off has just occurred right at the end of the channel at the drain.

  • We say that at this value of VDS, we are entering the saturated region:

MOSFETs


Fet operation quantitative7
FET Operation - Quantitative

  • If we know what value of VDS produces saturation, then we can use this to develop an equation for the maximum current that can flow.

VGS-VT

  • but

  • therefore

MOSFETs


Fet operation quantitative8
FET Operation - Quantitative

  • At low voltages we can simplify the equation that bit more, if we assume that VDS is very small, then we can assume the square of a small number is very small.

  • The practical reality of this is that the values of VDS for which this is accurate are very small and won’t be of any practical design interest.

  • However as VDS increases it moves from a region where this is valid to the saturation region, so for a while it still approximately true, but increasingly less true as VDS increases.

MOSFETs





Channel length modulation
Channel Length Modulation

Metal

Source

Drain

N

N

L’

L

  • When we were working out the performance of the MOSFET at high VDS we make the assumption that once pinch-off has occurred then the current hits it’s maximum and stays constant. This is sort of true but there is another mechanism involved that is very significant in modern CMOS designs.

MOSFETs


Channel length modulation1
Channel Length Modulation

Metal

Source

Drain

N

N

VDS(sat)=VGS-VT

L’

L

VDS- VDS(sat)

  • Across the channel, only VGS-VT can be dropped because once this voltage has been dropped then the channel ceases to exist.

  • The remain of the externally applied VDS needs to be dropped across something else, and this is the depletion region that forms near the DRAIN node.

MOSFETs


Channel length modulation2
Channel Length Modulation

Metal

Source

Drain

N

N

L’

L

  • Across the channel, only VGS-VT can be dropped because once this voltage has been dropped then the channel ceases to exist.

  • The remain of the externally applied VDS needs to be dropped across something else, and this is the depletion region that forms near the DRAIN node.

  • In these cases the inverted layer is separated from the drain node by a depletion region.

MOSFETs


Channel length modulation3
Channel Length Modulation

Metal

Source

Drain

N

N

L’

L

  • Now carriers that have been travelling through the inversion region are travelling so fast that they are injected into the depletion region and are travelling fast enough to get swept across the PN junction.

  • The carriers at this point are minority carriers at a reverse biased PN junction and hence are swept across the junction if they get close to the junction. The speed of the carriers is such that they do get to within one diffusion length of the junction.

MOSFETs


Channel length modulation4
Channel Length Modulation

Metal

Source

Drain

N

N

L’

L

  • The practical effect of this is that we do not need to include the L term indicated in the diagram, so the effective L’ left to be traversed is

  • But the width of the depletion region is dependent on the applied reverse-bias voltage which is some fraction of VDS . It could be worked out from the equations for the depletion width.

MOSFETs


Channel length modulation5
Channel Length Modulation

  • However this isn’t of great importance, the important fact is that L’ is smaller than L which means that

  • Which means that the saturation current will increase.

  • This variation in L has been analysed and it is possible to model this effect with the following modification to the the saturation current equation.

 is always positive

MOSFETs


Channel length modulation6
Channel Length Modulation

  • Values of  range from 0.005 to 0.03 however  is increasing in more modern devices as the geometries get smaller.

  • Actually  has a correspondence to the Early Voltage in BJT’s and actually the same term is used. Early Voltages in FET’s are in the range of 30 to 200 V. The large the early voltage the flatter the saturated region current curve.

  • The effect of smaller geometries can be quickly demonstrated by the ratio

Bigger VA the better.

MOSFETs


Channel length modulation7
Channel Length Modulation

Bigger VA the better.

MOSFETs


Body effect
Body Effect

  • Another very important second order effect is the body effect. The effect of this is to vary the threshold voltage.

  • The body effect occurs when the substrate of the transistor (in which the channel forms) is not at the same voltage as the source.

MOSFETs


Body effect1
Body Effect

  • We’ve assumed so far that the source and substrate have been connected. If they are not connected then they must be reverse biased.

  • If they are not reversed bias then the PN junction caused by the substrate and source regions will be forward biased and the transistor will not operate.

  • If they are reversed biased then a larger depletion region will form between the two regions. This will introduce additional depletion region charge which the applied gate voltage will need to overcome to achieve inversion. Thus the threshold voltage will increase.

MOSFETs


Body effect2
Body Effect

  • Now we said that in an NMOS, the P channel bulk is normally tied to ground.

  • In a PMOS, the N channel bulk is normally tied to the positive voltage supply and the source if it drops below the positive voltage supply voltage will begin to affect the threshold voltage.

  • This is to ensure that all substrate-to-channel junctions are always reverse biased or at least unbiased. It helps prevent latch up and unplanned current paths.

  • If this approach is taken, it avoids having to check continually to ensure that all PN junctions in the MOSFET are correctly biased. A good design tactic.

MOSFETs


Body effect3
Body Effect

  • Almost always in a design the bulk and source of the transistors are always tied to the same voltage, and normally the most positive (PMOS) or negative voltage (NMOS).

  • If this were not the case then the source would vary according to the signal on the gate, which would then vary the source-bulk voltage which would affect the threshold voltage which would affect the biasing of the transistor which would affect the gain of the device. This could lead to very poor performance.

MOSFETs


Hybrid model
Hybrid  Model

iG

iD

Gate

Drain

+

vGS

-

+

vDS

-

gmvGS

rds

Source

  • This is a simplified version of the Hybrid-  model presented that was used for the BJT. The most obvious lack is any input resistance, this is because we have an insulated gate and there is no DC current path.

  • The two remaining important parameters are gm and rds. These can be obtained from the large signal current equation for ID

MOSFETs


Small signal modeling
Small Signal Modeling

  • gm is defined as the small signal partial derivative of output current with respect to input voltage, ie

  • Therefore as

MOSFETs


Small signal modeling1
Small Signal Modeling

  • Now for the triode region as before it is possible to determine gm. This is a region in which the output current and voltage are acting like a resistor, so gmwill be expected to have a dependency on VDS

Same gm as in the

saturated region when

VDS reaches saturation.

MOSFETs


Small signal modeling2
Small Signal Modeling

  • It is normal to attempt to rewrite the small signal parameter equations in terms of physical signals that we can control. This allows us to develop a feel for how we can bias the circuit.

  • gm is most important when we are operating in the saturated (active) region so we’ll look at that.

  • To keep things simple, we’ll temporarily ignore channel modulation effects.

MOSFETs


Small signal modeling3
Small Signal Modeling

  • therefore

  • So

  • Similarly

MOSFETs


Small signal modeling4
Small Signal Modeling

  • gm is a very important term and is a major factor in the gain of any circuit, so to recap, let’s consider how it changes with respect to our bias conditions.

Increase the gate voltage, you

linearily increase the gain.

Increase the drain current, you

increase the gain by only a

square-root factor.

Note:

MOSFETs


Small signal modeling5
Small Signal Modeling

  • The remaining parameter in this simple model is rds. Now rds is defined as the partial derivative of output voltage to output current (as it’s small signal).

  • If we look at the saturated (active) region where the FET is most commonly used.

  • therefore

MOSFETs


Small signal modeling6
Small Signal Modeling

  • Now, if  is small, ie a small second order relationship between IDsat and VDS, then we can make a simplifying assumption, that the IDsat current is constant and equal to Idsat.

If  is small, and it is normally so, then rds is the reciprocal of a small current by a very small number, resulting in a very large small signal resistance.

MOSFETs


Small signal modeling7
Small Signal Modeling

  •  is an indicator of the degree to which the depletion region around the drain gate of the MOSFET modifies the overall channel length.

  • A high value of  indicates a large degree of modulation.

  •  can be reduced linearly by increasing the length of the device that you are designing. So to obtain higher output resistance, use a longer device.

MOSFETs


Small signal modeling8
Small Signal Modeling

  • In the triode region, we have a different expression for current and it indicates a simple resistor relationship. We’d expect something similar for the small signal resistance.

MOSFETs


On resistance r ds and r ds
On Resistance, rDS and RDS

Looking at the two values for rds we can compare their respective values

Assume =1 for a moment, and assume VOD=1 as well, then the saturation value is just twice that of the triode resistance.

If VOD is less than one, the saturation resistance is larger again due to the inversion effect. If VOD larger then the saturation resistance is smaller.

MOSFETs


On resistance r ds and r ds1
On Resistance, rDS and RDS

However let’s consider a real circuit,

This means that assume VOD = 1 (for simplicity) then the small signal saturation region resistance can be significantly greater, often 100 times greater than in the triode region.

MOSFETs


Small signal modeling9
Small Signal Modeling

  • Now we have expressions for both parameters in our model in the two areas of interest.

  • This fully defines the small signal model but it is useful at this point to consider the large signal, or more precisely, the DC value of output resistance that is presented by the transistor.

  • The small signal output resistance was indicated by the inverse of the slope of the ID vs VDS characteristic curve, but the DC resistance is simply the ratio of the two. This indicates that we’ll be expecting a difference between the AC and the DC resistances for the MOSFET.

MOSFETs


On resistance r ds
On Resistance, RDS

The DC current for small voltages in the triode region is given below

Given this, it is possible to work out what the DC resistance RDS would be

MOSFETs


On resistance r ds1
On Resistance, RDS

  • In the triode region, the small and large signal channel resistances, the drain-source resistance, are approximately the same.

    • The same slope applies for a small change in the signal as for the overall ratio of overall signal current and voltage.

  • Thus when operating in this region, the same drain-source resistance can be used for small signal (rDS) and for DC applications (RDS)

MOSFETs


On resistance r ds2
On Resistance, RDS

Let’s consider the on resistance for DC current just at pinch-off. At pinch-off, the current is given as

But it should be noted that

Thus

Twice RDS(triode)

MOSFETs


On resistance r ds3
On Resistance, RDS

In saturation, the current increases only a little with increase VDS, (assuming channel modulation) so this means that the drain-source resistance is going to rise.

The current in the saturation region is given by

Thus

MOSFETs


On resistance r ds4
On Resistance, RDS

If we look at the circled term, when VDS=VOD then this RDS is the same as that at pinch-off.

As VDS increases however the circled term increases linearly, indicating an increase in device resistance.

The other term is due to channel modulation and it allows additional current to flow and it effectively reduces the resistance a little but it is the weaker of the two terms.

But remember, this is still a small resistance as the currents can be quite large for some selections of VOD and VDS.

MOSFETs


On resistances r ds and r ds
On Resistances, rDS and RDS

  • The saturated region has a high small signal on resistance, rDS, and a low large signal resistance RDS. The high small signal resistance comes from the small slope on the graph,

    • a small change in voltage, vDS, will produce a very small change in current iDS.

  • It has a small large signal on resistance, RDS because for a given VDS it is producing a relatively large amount of current.

  • This difference in RDS and rDS is very useful in designing FET circuits as we can use the smaller RDS for biasing and the large rDS for small signal gains.

MOSFETs


Example
Example

Calculate the effective resistance between source and drain for a N channel MOSFET transistor with the following characteristics

VDS = 0.1 V

VT = 1.0 V

VGS = 5.0 V

nCox = 0.2 mA/V2

W = 5.0 m

L = 0.25 m

 = 0.01

Calculate the effective DC and small signal resistance if VDS was increased to 6 V.

MOSFETs


Example1
Example

To calculate the effective resistance is a simple case of adding in the numbers.

MOSFETs


Example2
Example

Now from the equation we need to find RDS(pinch) but we know it’s twice RDS(triode) for the same VOD.

Now ID(pinch)

MOSFETs


Example3
Example

Note: the factor of 10 difference in the resistances.

MOSFETs


Switching applications
Switching Applications

Large DC signal MOSFET applications are very important. In reality they are some of the most important circuits in electronics.

The main characteristic that you need to remember is that the MOSFET is a very good switch.

When the device is FULLY ON, ie the VGS is at its maximum value, the on-resistance of the circuit, both AC and DC is relatively low.

When the device is FULLY OFF, VGS is at its minimum value, the on resistance of the circuit, again AC and DC is near infinite. (No inversion channel, no conduction).

The main switching circuits that you’ll encounter are transmission gates and logic gates.

MOSFETs


Switching applications1
Switching Applications

To turn a MOSFET fully off, you want to remove ANY inversion region that may exist.

A strong inversion region occurs when the gate-channel voltage exceeds the threshold voltage.

Assuming NMOS

However a weak inversion channel can occur below this.

To ensure that there is no channel, set the gate voltage to the lowest available voltage, less than or equal to the source and bulk voltages. (Note source voltage has to be greater than bulk). This guarantees that no charge is attracted to the gate, no chance of an inversion region.

Assuming NMOS

MOSFETs


Switching applications2
Switching Applications

To turn a MOSFET fully on, you want to maximise the inversion region. This occurs when the gate-channel voltage is at it’s maximum possible value (Assuming NMOS).

A strong inversion region occurs when the gate-channel voltage exceeds the threshold voltage.

Thus the maximum VOD will ensure the minimum RDS (and co-incidentally rds).

MOSFETs


Signal gates switches
Signal Gates/Switches

Control 1

Signal 1

Control 2

Signal 2

Output

Control 3

Signal 3

In analog circuitry it is always very useful to be able to disconnect signals and reconnect them.

For example the multiplexor

MOSFETs


Signal gates switches1
Signal Gates/Switches

Control 1

Signal 1

Control 2

Signal 2

Output

Control 3

Signal 3

In a digital system, you could use AND gates to control the multiplexor. If you ANDed your signals with your control signals, the input would only get to the output IF the control signal was set to 1.

However in practice you’d need to do a few other things first because you can’t have an output of a 1 and 0 on the same wire. The principle is okay though.

MOSFETs


Signal gates switches2
Signal Gates/Switches

In the analog world, the input signals are continuous in value, or in simple terms, they may take any value in the range available.

So if the range was 0 to 1, they may take 0.44554 or 0.7. All are equally valid. Therefore LOGIC type switches are not acceptable.

What we need to aim for is a physical representative of the ideal switch.

MOSFETs


Signal gates switches3
Signal Gates/Switches

Zero Resistance

Infinite Resistance

Zero / Low / Infinite

Zero / Low / Infinite

Zero / Low / Infinite

Zero / Low / Infinite

MOSFETs


Signal gates switches4
Signal Gates/Switches

Now a single transistor switch can be very useful. Quite often they are used in powerdown circuits or to turn off sections of a circuit.

Powerdown circuits work by setting the gates of transistors to their FULLY OFF values. This means that any amplification or transistor action is turned off.

The switch is placed between the gate and ground (NMOS) or VDD (PMOS).

This does mean that there is a low resistance path to ground/VDD which if not designed for could lead to large currents feeding back to the source of the input signal.

MOSFETs


Signal gates switches5
Signal Gates/Switches

PMOS’s are best used to pull signals to the high voltage rail.

NMOS’s are best used to pull signals to the low voltage rail.

Note: The same powerdown signal could not be used to control both transistors.

MOSFETs


Signal gates switches6
Signal Gates/Switches

Single transistor switches can be also be used inline to disconnect a signal.

Note bulk tied

to ground.

However the problem then is that there is now a section of wire that is floating. We don’t know what voltage it is?

This is very bad as parasitic capacitances, CGS, CGD, may charge up, turning the NMOS’s on, or even blowing transistors (pumping effect).

MOSFETs


Signal gates switches7
Signal Gates/Switches

The solution to this is to ensure some other circuit element controls the voltage at this node.

In a powerdown circuit, we could add the powerdown transistor. Then the inline transistor protects the input from any current flow to the ground or from the positive supply.

In a multiplexor, one other gate should always be selected, a default one if necessary and this would control the voltage on the wire at the source side of the inline transistor.

The following two pages have a powerdown circuit and a multiplexor.

MOSFETs



Signal gates switches9
Signal Gates/Switches

NOTE: this circuit will work for certain signals.

MOSFETs


Signal gates switches10
Signal Gates/Switches

We need to look at the inline transistor in a little more detail.

NMOS

Gate

VGS

Source

Drain

VSB

Bulk

When this is fully on, we want it to present little resistance to the signal. So what we need to ensure is that VGS>VT and that the source voltage is always greater than the bulk

MOSFETs


Signal gates switches11
Signal Gates/Switches

Gate

VGS

Source

Drain

VSB

Bulk

Okay.. The first thing to do is wire the bulk to ground. This ensures that the Source-Bulk PN junctions remains reverse biased.

The second thing we need to do is consider the range of voltages that the signal on the source can experience.

MOSFETs


Signal gates switches12
Signal Gates/Switches

Imagine that we are turning this gate on, so VG=5V. Let’s assume it’s a 0-5 V system, the signal can go from 0-5V and that the VT of our transistor is 2.5 V.

So the critical voltage to watch is VGS. This is

MOSFETs


Signal gates switches13
Signal Gates/Switches

Now what this chart would indicate is that the impedance of the transistor is small when Vsignal is small. This is because

VGS = 5 - Vsignal > VT (1V)

But if Vsignal increases, then VGS decreases and the impedance slowly rises and then shoots up in sub-threshold and hits infinity when there is insufficent VGS for an inversion region.

MOSFETs


Signal gates switches14
Signal Gates/Switches

So basically if the input goes too high, the transistor will begin to turn off even when we have the gate voltage at it’s maximum value.

This puts an upper limit on the maximum value for the input signal for which this transistor is an acceptable switch.

However we never want to waste voltage range like this. Reducing the allowed voltage range, reduces our maximum SNR (signal-to-noise ratio).

A solution to this problem is to use a second transistor.

MOSFETs


Transmission gate
Transmission gate

Note: Sources

connected.

This circuit consists of a PMOS and an NMOS. The inverter is present to change the control signal from a 5 to a 0 (logic 1 to 0) and visa-versa.

This is needed because to turn a PMOS on, we need VG=0 (remember opposite way) and for the NMOS on, VG=5.

MOSFETs


Transmission gate1
Transmission gate

The transistors can be modeled as variable resistors, and they are in parallel.

MOSFETs


Transmission gate2
Transmission gate

Control Voltage = 5V

PMOS

NMOS

Combined

Now we know that when the signal when high, the NMOS was high impedance. However the PMOS has the opposite effect. It requires the signal (source) to be higher than the gate (which is now 0V) and so it shows a low impedance.

The parallel combination ensures that irrespective of the signal value, the impedance when the transistors are turned ON is very LOW.

MOSFETs


Transmission gate3
Transmission gate

The standard symbol for the transmission gate is

Indicates Inverted

signal for PMOS

When drawn like this, when the control signal goes high, the gate is closed (LOW resistance). High gate voltage, low resistance. Low gate voltage, infinite resistance.

Note: The symbol is symmetric. Remember the structure of the MOSFET, there is no difference between source and drain so generally you can wire this anyway you like, input on either side.

MOSFETs


Transmission gate4
Transmission gate

  • Threshold Voltage

    • Transmission gates work best when the threshold voltage is not in the centre of the range (eg 2.5V for a 5V range) because you want one transistor definitely ON when the other is turning off/on.

  • ON Resistance

    • The on resistance of the transmission gate can be made very low. This is useful as we do not wish to add more resistance to a circuit, as all nodes have some capacitance and the charging up time is based on RC.

    • Normally the ON resistance is dependent on the application, some where speed and current flow are not issues the on-resistance can be quite high. It is often a trade-off between speed and size, high speed, big devices.

MOSFETs


Transmission gate5
Transmission gate

  • Clock Feedthrough

    • There is an issue with something called clock feedthrough which is based upon capacitances and transistor speed. It is only a significant issue at high frequencies. Basically what happens is that the junction capacitances charge and discharge at different rates and hence the voltages may change at different rates.

    • A good solution is to keep the sizes of the devices equal so that capacitances remain approximately the same. For highly sensitive systems, further factors can be also considered.

    • This is a third year/fourth year concern.

MOSFETs


Example4
Example

Design a switch capable of being driven by a 0/2.5V logic signal that can switch an input signal that ranges from 0.3 to 2.2 V. The effective resistance of the switch when open should exceed 100 M and when closed should present no more than 25.

PMOS NMOS

VT = 0.8 V VT = 0.8 V

mpCox = 30 mA/V2mpCox = 90 mA/V2

lp = 0.05 lp = 0.05

Minimum device length = 0.18um

MOSFETs


Example5
Example

First: The voltage range of the input is such that it goes below 0+VT for the NMOS and 2.5-VT for the PMOS. So a single transistor switch would be unsuitable for the task. The transistor would be turned off by the input signal. Therefore you must use a transmission gate.

Second: the off-resistance of a transmission gate is the parallel resistance of two devices with no inversion region, hence two reverse bias diodes. It’s going to be big.. So let’s say the off condition has been satisfied.

MOSFETs


Example6
Example

  • Third: The ON resistance is the parallel combination of two resistances. Considering the curves of the transistor resistances, we have two situations

    • The extremes, one very large and one very small resistance.

    • The centre, two small but significant resistances in parallel.

  • In calculating these resistances, assume the device is in the triode region, a very low resistance ideally (<20 ohms) by a small current, less than 10mA (which is a large current) gives you a VDSof less than 200mV.

MOSFETs


Example7
Example

Pick the extreme, from the equation, the PMOS will have the bigger resistance due to the smaller mobility (mCox = 30mA/V). So if we satisfy the PMOS-on extreme, then the NMOS-on side will be satisfactory too.

Now at the extreme, Vsignal=0, VG=2.5, VT=0.8 so

Therefore

MOSFETs


Example8
Example

Pick the centre, here we need to calculate both the NMOS and the PMOS transistor resistances.

In the centre, Vsignal = 1.25, so

For this example, it just happens to be the same for P and N.

Therefore

MOSFETs


Example9
Example

Now the centre is the parallel resistance of two devices so

MOSFETs


Example10
Example

So now we have two constraints for us to satisfy our maximum resistance requirements.

Centre

PMOS extreme

So the PMOS extreme is the tougher one, so set W/L to be 1000, safe enough.

Use minimum length for L, giving

This is a BIG device.

Finally, we did not factor in temperature or variations in process (mobility), which would require us to make the device even bigger and test more extremes or corners.

MOSFETs


Digital logic
Digital Logic

Before we look at circuits, there’s a couple of points worth clarifying at this point.

The transistors in the following circuits can be considered as SWITCHES once they have changed state.

For the moment we shall not worry about what happens when they are changing state.

There will be no floating nodes anywhere in these circuits.

MOSFETs


Digital logic inverter
Digital Logic - Inverter

In the inverter, the NMOS source is tied to ground, the PMOS source is tied to VDD. So when we gave a gate voltage, there is no issue of what VGS is.

MOSFETs


Digital logic inverter1
Digital Logic - Inverter

100 M

10 k

Consider a logic 1 input (high voltage).

PMOS VGS = 0, PMOS is OFF

high resistance

NMOS VGS = VDD, NMOS is ON

low resistance

Voltage divider theorem says that the output voltage is going to be effectively zero (Logic 0)

MOSFETs


Digital logic inverter2
Digital Logic - Inverter

10 k

100 M

Consider a logic 0 input (low voltage).

PMOS VGS = VDD, PMOS is ON

low resistance

NMOS VGS = 0, NMOS is OFF

high resistance

Voltage divider theorem says that the output voltage is going to be effectively VDD (Logic 1)

MOSFETs


Digital logic inverter3
Digital Logic - Inverter

Now consider it when we have set a value on our input, either high or low. What is the current flowing through the two transistors?

MOSFETs



Digital logic inverter5
Digital Logic - Inverter

  • In summary:

    • Current only flows when the inverter is changing state.

    • If it is in either state NO current flows.

    • If it is between states then you have a low resistance path between the supply and earth and you have a VERY LARGE current flow. This has large thermal consequences.

    • An input midrange for an inverter, and as we shall see, any logic gate, is very dangerous and likely to lead to destruction of your transistor and chip.

MOSFETs


Digital logic inverter6
Digital Logic - Inverter

  • Total energy dissipated depends on the maximum power during transition and how long it took for the transition to occur.

  • To minimise the dissipated energy,

    • Ensure that the inverter changes state rapidly by ensuring that there isn’t excessive capacitance on the output for the transistors driving it.

    • Increasing the ON resistance so that the maximum current that can flow is limited.

    • Reduce operating frequency.

MOSFETs


Digital logic inverter7
Digital Logic - Inverter

  • Capacitance in a Logic Circuit

  • Capacitance on the output of the inverter is probably the major factor in determining the speed of the inverter.

  • The capacitors on the output need to be charged up, the more current you can pump into the capacitor the faster it charges, or similarly the smaller the series resistance the smaller the RC time constant.

  • The capacitance normally comes from the parasitic capacitance connected to the gates of the transistors it’s connected to, CGS and CGD. There are also parasitic capacitances from wires passing near other pieces of metal.

MOSFETs


Digital logic inverter8
Digital Logic - Inverter

  • Capacitance in a Logic Circuit

  • To reduce the effect of capacitance you need to supply more current to the output capacitors… ie. You need to reduce the series resistance connected to the output,

  • This is called giving the transistors more drive, the ability to drive current where you want to.

  • Increasing W/L increases the current that can flow for a given VOD. These transistors never enter saturation. If you want to look at it another way, increasing W/L decreases the resistance too.

MOSFETs


Digital logic inverter9
Digital Logic - Inverter

  • Capacitance in a Logic Circuit

  • The only problem with this solution is that the maximum current that can flow while switching between states now has increased because you’ve effectively decreased the transistors resistances.

  • As always, it’s a trade-off. If you want to operate at high frequencies, you need to either

    • Reduce output capacitance and maintain the same power loss levels. However reducing output capacitance means that you are not able to drive as many gates with one output.

    • Maintain the output capacitance and use more current, dissipate more power.

MOSFETs


Digital logic inverter10
Digital Logic - Inverter

  • Sizing the Transistors

  • To get a symmetric response, you need to consider the different response rates of the N and P MOSFETs. If one is faster than the other then you may find that going from 0 to 1 (rising edges) and 1-0 (falling edges) may have different rates of change.

  • The drive, on-resistances of the MOSFET is dependent on W, L and . COX can be assumed to be the same, it’s just SiO2.

  • However n is about 3 times greater than p so often to get the same response for rising and falling edges, the PMOS is made larger.

MOSFETs


Digital logic inverter11
Digital Logic - Inverter

  • Delay in the Inverter Cell

  • To get a symmetric response, you need to consider the different response rates of the N and P MOSFETs. If one is faster than the other then you may find that going from 0 to 1 (rising edges) and 1-0 (falling edges) may have different rates of change.

  • The drive, on-resistances of the MOSFET is dependent on W, L and . COX can be assumed to be the same, it’s just SiO2.

  • However n is about 3 times greater than p so often to get the same response for rising and falling edges, the PMOS is made larger.

MOSFETs


Delays in the inverter
Delays in the Inverter

  • There are three sources of delay in a logic gate.

    • starting delay

    • rise time delay

    • ripple delay

  • A modern logic gate delay would be in the order of 0.1 ns. This corresponds to 10GHz. To get real 1GHz operation, you need a factor of 10 at least on your delay, so 0.1 ns.

  • Most manufacturers don’t get these speeds, but some specialise in high speed digital-use transistors, for example INTEL, AMD, IBM.

MOSFETs


Delays in the inverter1
Delays in the Inverter

  • Starting Delay

  • This occurs because the input needs to rise past the devices’ threshold voltage prior to the transistors beginning to react to the change in input. Basically one of the transistors needs to start turning off and the other on.

  • The rate of change of the input is dependent on the amount of capacitance on the wire connecting to the gates and also on the current driving ability of the input. A higher drive input will change faster.

  • A solution is to either reduce capacitance, ie drive less devices in parallel or to reduce the threshold voltages of the transistors so that they start turning on and off quicker.

MOSFETs


Delays in the inverter2
Delays in the Inverter

  • Starting Delay (cntd)

  • Normally threshold voltages for logic devices are kept the same and at the centre of the range. This minimises the time that both transistors are on at the same time, ie wasting power.

  • If the threshold voltages were reduced, the devices would react quicker when turning on, (0->1V) but slower when turning off ( 5V-1V). Thus the output would begin to change, approach the middle of the range but at the expense of more power.

  • Similar if the threshold voltages were increase, the devices would turn off quicker but turn on slower. This leaves a gap in the middle were the output is undriven, a floating node. It could go to any voltage, so less power, but no improvement in reaction time.

MOSFETs


Delays in the inverter3
Delays in the Inverter

  • Rise Time Delay

  • Rise time delay is the delay that arises due to the speed at which the output can change state. Equally it’s a measure of how fast we can turn the transistors on and off. The speed is normally limited by the capacitors on the output node.

  • The more capacitance, the greater the time constant RC. Capacitance comes from the wires themselves but more importantly the logic gates connected to the output. The more devices you connect to the same output the more capacitance, the slower the logic.

  • For fast operation, connect fewer devices to each output.

  • The other solution is to design your logic gates transistors to have greater drive, this means the ability to supply current, equally to reduce RC. This uses more power. Again the power and speed trade-off.

MOSFETs


Delays in the inverter4
Delays in the Inverter

  • Ripple Delay

  • When the transistor changes state there is a resulting transient oscillation. This comes from parasitic inductances from the wires, the capacitance and the resistances. It decays away rapidly but while it is decaying, there is an uncertainty about the value of the output. The time it takes to decay needs to be factored in.

Input

Output

MOSFETs


Delays in the inverter5
Delays in the Inverter

  • Ripple Delay (Cntd)

  • As it is an RLC oscillation, increasing the capacitance will lower the frequency of the oscillation, requiring it to take longer to settle. As resistance is the damper on the oscillations, reducing it increases the size of the oscillations and their length. It is a trade-off, but it can be generally taken care off my reducing the capacitance on the node and by not using too high a drive (low resistance) devices.

  • The biggest problem with this ripple is the bad outputs. In clocking systems if this is not taken care off you may get, for some rapid responding logic gates, a false output and thus clock some registers but not others.

MOSFETs


Quick thoughts on logic gates
Quick Thoughts on Logic Gates

  • Consider all gates to be combinations of perfect switches.

  • If a MOSFET is on, think of it as a shorted wire. If it is off, think of it as an open section of wire.

  • Everything is based off the inverter.

  • The output must never be left as a floating node or connected as a floating node.

  • Consider the top (PMOS) and bottom (NMOS) sections of the logic gate as separate and needing to individually satisfy the logic truth table.

  • The logic gates are constructed from combinations of transistors in parallel or in series.

MOSFETs


Quick thoughts on logic gates1
Quick Thoughts on Logic Gates

  • Parallel Combinations

  • When two or more devices are connected in parallel, then only one needs to be ON for the parallel combination to be ON.

  • This is useful for OR type functions.

  • Series Combinations

  • When two or more devices are connected in series, then only one needs to be OFF for the parallel combination to be OFF.

  • This is useful for AND type functions.

MOSFETs


Nand gate
NAND Gate

  • NAND Logic Table

  • A B | Y

  • -------+---

  • 0 0 | 1

  • 0 1 | 1

  • 1 0 | 1

  • 1 1 | 0

  • In english, when both are high, we need the output pulled low, or else the output should be tied high.

  • HINT:

  • ALL inputs high for low output, indicates series combination for N’s

  • ANY input low for high output, indicates parallel combination for P’s.

MOSFETs


Nand gate1
NAND Gate

MOSFETs


Nor gate
NOR Gate

  • NOR Logic Table

  • A B | Y

  • -------+---

  • 0 0 | 1

  • 0 1 | 0

  • 1 0 | 0

  • 1 1 | 0

  • In english, when both are low, we need the output pulled high, or else the output should be tied low.

  • HINT:

  • ALL inputs low for high output, indicates parallel combination for P’s

  • ANY input high for low output, indicates series combination for N’s.

MOSFETs


Nor gate1
NOR Gate

MOSFETs


Multiple inputs nor
Multiple Inputs NOR

  • NOR Logic Table

  • A B C | Y

  • -------+---

  • 0 0 0 | 1

  • 0 0 1 | 1

  • 0 1 0 | 1

  • 0 1 1 | 1

  • 1 0 0 | 1

  • 1 0 1 | 1

  • 1 1 0 | 1

  • 1 1 1 | 1

  • ALL inputs low for high output, indicates parallel combination for P’s

  • ANY input high for low output, indicates series combination for N’s.

MOSFETs



The rs latch
The RS Latch

  • Flip-Flops come in many different forms. The most basic or primitive form of flip-flop is the RS latch. A latch is only half of a flip-flop, it doesn’t have timing but it does lock a state.

  • Now let’s rewrite the NOR logic table.

  • A B | Y

  • -------+---

  • 0 0 | 1

  • 0 1 | 0

  • 1 0 | 0

  • 1 1 | 0

MOSFETs


The rs latch1
The RS Latch

  • S=0, R=0, Q=0, QB=1 S=0, R=0, Q=1, QB=0

  • Complete Logic table,

  • S R | Q QB

  • -------+------

  • 0 1 | 0 1

  • 1 0 | 1 0

  • 1 1 | U U

  • If inputs S=0, R=0, Q and QB don’t change.

MOSFETs


The rs latch2
The RS Latch

  • The only state that is not well defined is the 1-1 input condition. If this condition is avoided then there is never a problem with the SR latch.

  • Note: The function of this signal is independent of any external timing. Once an input comes in, it stabilises on a steady output.

  • If the inputs are then removed, the Q and QB feed back signals maintain the outputs as required, maintaining the signal.

  • Another implementation of this is using NANDs. No significant difference but it’s slightly easier to use this version in practice.

MOSFETs


The sr flip flop
The SR Flip-Flop

  • This is the prototype of the JK flip-flop and it is a simple derivation from the latch. The only difference is that a clock signal is used to gate (control) the inputs.

  • The right-hand part is an RS Latch so if the inputs go low, the output stays in its existing state.

  • The clock signals are ANDed. When they are high, the S R signals are allowed to be high or low, and thus effect Q and QB. When the clock signal is low, S R are held low, and Q and QB remain the same.

  • The outputs only change when the clock signal is high.

MOSFETs


The sr flip flop1
The SR Flip-Flop

  • It is possible to implement the RS flip-flop in a different manner using a transmission gate.

MOSFETs


The sr flip flop2
The SR Flip-Flop

  • The advantages of this implementation is that the delay of the gate is halved.

  • Transmission gates do not introduce delays.

  • First the Set-Reset signals enter and the first latch is readied prior to the clock signal.

  • When the clock signal occurs the steadied results are passed to the second SR latch and the final output is produced.

  • Between the change in the clock signal, only one pair of logic gates need to settle for a good output instead of the previous two.

  • At the expense of two transmission gates, the speed of the flip-flop has been doubled.

  • To ensure that the SB, RB signals are in a safe state, you can add another pair of transmission gates to tie these nodes to VDD (Logic 1) when the clock signal is low.

MOSFETs


The sr flip flop3
The SR Flip-Flop

  • The advantages of this implementation is that the delay of the gate is halved.

MOSFETs


Example11
Example

  • Design a circuit that would satisfy the following Boolean algebraic expression, displaying all necessary transistors. Boolean simplifications are allowed provided they are done correctly. Clearly indicate the type of transistor used. Explain the reason for the positioning of your transistors. Transistor parameters and sizes are not needed.

MOSFETs


Example12
Example

  • Let’s translate this into NANDs and NORs

  • Two NORs, one NAND and one INVERTER.

MOSFETs


Example13
Example

MOSFETs


Current mirror
Current Mirror

  • The current mirror is one of the most common amplifier circuits used. It is used primarily in biasing.

  • In biasing, the circuit is used to either sink (draw current into it) or source current (provide current from it) that will then be passed through over devices to set them into a particular operating regime.

Source (PMOS)

Sink (NMOS)

MOSFETs


Current mirror1
Current Mirror

  • The current mirror circuit is constructed as follows (NMOS example)

Input

Current

Reproduced

Current

D

G

S

  • The important thing is the wire connecting the drain to the gate. This guarantees that the transistor on the left hand side (the input device) is in saturation.

MOSFETs


Current mirror2
Current Mirror

Input

Current

  • With the short circuit, the drain is connected to the

  • gate, therefore

  • But saturation occurs when

  • However VDS is equal to VGS so as VT is a positive number, the device must always be in saturation.

MOSFETs


Current mirror3
Current Mirror

Input

Current

  • Now with the transistor in saturation, let us consider a transistor without channel modulation, then the saturation region current equation is given by

  • With a current being forced through the transistor, the gate voltage will adapt such that the above equation is satisfied. The short circuit between drain and gate ensures that the device remains in saturation.

  • The device is being controlled by the base current and not the gate voltage. Control one, you can control the other.

MOSFETs


Current mirror4
Current Mirror

  • Now consider a transistor that has the same value of W and L, the same mobility, threshold voltage, oxide capacitance, an identical transistor.

  • If that device is in saturation, then applying the gate voltage of the first transistor will force the second transistor to produce a current of the same size as the input current.

  • As it is in saturation, the value of the drain voltage on the second transistor is not important as in saturation the drain current is independent of the drain source voltage (in the ideal MOSFET)

  • So if we connect the two gates, we get the following circuit.

MOSFETs


Current mirror5
Current Mirror

Input

Current

Iin

Iout

Reproduced

Current

Iin=Iout

  • Assuming no channel length modulation

  • Assuming second device in saturation.

MOSFETs


Current mirror6
Current Mirror

  • The real benefit of this circuit comes from the nature of the MOSFET’s GATE. As no current flows into the gate of a MOSFET, for low frequency, DC applications, where capacitance is not an issue, connecting a hundred gates to the same input makes no circuit difference.

  • If the gate of the input device was connected to 100 mirroring transistors each one would produce an identical matched current, provided they were in saturation.

  • This allows circuit designers to obtain a single current and replicate it wherever and however often they wish.

MOSFETs


Current mirror7
Current Mirror

  • The value of the drain voltage of the mirroring transistor will be decided by the circuit that you connect to it.

  • You must design it so that there is sufficient voltage remaining in your circuit so that it will remain in saturation. If there is insufficient voltage, the device will leave saturation and the linear relationship between the two devices will change.

MOSFETs


Current scaling
Current Scaling

  • These two equations indicate that if the W/L ratios are the same, then for the same VGS, the same current will flow.

  • However, assuming the same VGS, if the W/L ratios were not the same, then we can scale the currents as follows.

MOSFETs


Current scaling1
Current Scaling

  • If we double the W/L ratio of the output transistor, the output current will double exactly. If we half the ratio, it will half. Any degree of scaling is possible.

  • Normally what is done instead of doubling the W/L ratio of the output device, we place two transistors in parallel, all terminals connected. Each will provide the same current. The combined result is the same as doubling the W value. It is however more precise as it is easier to match 3 identical transistors than to get one resistor precisely double that of another.

MOSFETs


Current mirrors and channel length modulation
Current Mirrors and Channel Length Modulation

  • Now in channel length modulation, the actual value of the drain-source voltage actually makes a difference.

  • Before we said it doesn’t matter if the drain-source voltage of the mirroring transistor was not the same as of the input device. This is not true in a real device.

  • There is a small VDS dependency which can typically add a 2% error per volt difference in VDS. In many applications this is not important, in others it can be.

MOSFETs


Current mirrors and channel length modulation1
Current Mirrors and Channel Length Modulation

  • Another way of looking at channel length modulation is to consider the small signal output impedance of the device.

  • For  small we need the ID curves in the saturation region as flat as possible. However the slope of the curves in the saturation region is 1/ro, the small signal output impedance.

  • The smaller the , the larger the small signal output impedance, the better the matching.

  • The output impedance of a single transistor is the small signal rds. In third year you’ll be taught techniques for using other circuits to massively enhance the effective rds to make better current mirrors.

MOSFETs



Biasing the mosfet
Biasing the MOSFET

  • Biasing of MOSFETs is easier than with BJT’s. There are two ways to bias a MOSFET.

  • Bias the gate such that it is over the threshold voltage and that you get the gm you desire. VDS is then designed such that you are in saturation or not.

  • Another technique is to pass a current through the device and let the device determine either the gate voltage or the drain source voltage.

  • For the single transistor amplifiers we’ll be looking at in this section, we’ll only be using voltage biasing.

MOSFETs


Biasing the mosfet1
Biasing the MOSFET

  • The best thing about voltage biasing a MOSFET is that there is no current passing through the gate into either the source or drain.

  • Once we know the VGS voltage we want, we just use a simple resistor divider to set it. The bigger the resistors the better to minimise the current flowing. Size actually doesn’t matter as no current flows into the gate.

  • The choice of VGS is determined by the need to exceed the threshold voltage and the value of ID or gm that you want for your applications.

MOSFETs



Biasing the mosfet3
Biasing the MOSFET

  • Life can be normally made easier by determining the region you want your transistor to be in, then you can simplify the ID equation.

  • Normally you want to be in saturation, thus

MOSFETs


Biasing the mosfet4
Biasing the MOSFET

  • For example, assuming a threshold voltage VT, you want the saturation mode and a current of ID as your DC current.

    • Note that

    • that VDS > VGS- V

    • and VDS = VDD - IDRD

  • Solve this by

    • calculating the required VGS.

    • Setting VDS be some number greater than VGS-VT

    • work out the value of RD such that at least that value of VDS will always be maintained.

    • Determine resistor divider network to get VGS

MOSFETs


Example14
Example

  • For the following circuit, calculate the values of RD, RB1, RB2, VGS, VDS to obtain a drain current of 3 mA in saturation mode. Assume the following device parameters:

  • Cox = 90 A/V

  • VT = 1 V

  • W/L = 20

MOSFETs


Example15
Example

  • 3mA of drain current in saturation mode

MOSFETs


Example16
Example

  • Quickly, the resistor divider network can be found.

  • Let RB2 = 283 k ohms

  • then RB1 = 217 k ohms

  • Any numbers will do.

MOSFETs


Example17
Example

  • Just as quick to find VDS

  • And to finalise it.

MOSFETs


Summary for dc biasing
Summary for DC Biasing

  • To determine the DC bias conditions, generally you need to know the current that you want to flow. This is provided or is a design issue.

  • Once you have this, you need to determine whether you want to be in saturation or triode. Most amplification action takes place in the saturation region.

  • Then calculate VGS. After that calculating the rest of the circuit is a case of satisfying the requires for your choice of region, eg saturation (VDS>VGS-VT)

MOSFETs


Mosfet amplifiers
MOSFET Amplifiers

  • There are three main types of MOSFET amplifiers.

    • Common source (the main amplifier configuration)

    • Common drain (also called source-follower)

    • Current Mirrors

  • Current mirrors aren’t exactly the same as the others as they require two transistors but it is possible to get accurate current amplification from them.

  • We’ll consider common source first and then source-followers.

MOSFETs


Common source amplifiers
Common Source Amplifiers

  • Common Source, both the input signal and the amplified signal share the same source path in their loops.

  • The small signal hybrid- model can be easily constructed.

MOSFETs


Common source amplifiers1
Common Source Amplifiers

rds

gmvgs

  • The bias resistors connect the gate to the source but they are so large that they won’t drain much current. Either way they don’t affect vgs, all of vgs is dropped across them anyway.

  • RD and the small signal output impedance are in parallel with each other, so the much large rds will normally be removed as being too large to be significant.

MOSFETs


Common source amplifiers2
Common Source Amplifiers

rds

gmvgs

  • In an ideal MOSFET, there is no current gain, because there is no input current path. The small signal input resistance is infinite.

  • We can only calculate the small signal output resistance and the small signal voltage gain.

  • In this simple circuit the answers are fairly obvious.

MOSFETs


Common source amplifiers3
Common Source Amplifiers

id

rds

gmvgs

  • Voltage gain is defined as

  • The output voltage is the voltage dropped across the parallel combination of the resistors.

MOSFETs


Common source amplifiers4
Common Source Amplifiers

id

rds

gmvgs

  • But vgs is the input voltage so

  • The small signal output impedance of the circuit is simply the parallel combination of the resistors

MOSFETs


Common source amplifiers5
Common Source Amplifiers

  • This circuit functions quite well as an amplifier however there is one problem with using this circuit. The gain of the circuit is totally dependent on the value of a device parameter gm. gm is controlled in a MOSFET much more than  is in a BJT as

  • However even though controllable, VT could change as can ID from device to device and from one temperature to another temperature.

MOSFETs


Source degeneration
Source Degeneration

  • Source Degeneration

  • This is very similar to Emitter Degeneration in the BJT and it has the same function, to remove the dependency of the circuit gain from gm.

MOSFETs


Source degeneration1
Source Degeneration

  • There are some important

  • things to note:

    • The input is from GATE to ground

    • The source is no longer ground

    • the drain resistor is from drain to ground, not to source.

Vgs

gmvgs

rds

Vg-ground

(input)

Vs-ground

MOSFETs


Source degeneration2
Source Degeneration

Vgs

ids

iD

gmvgs

rds

Vg-ground

(input)

Vs-ground

  • Voltage gain is defined as

  • The output voltage is defined by the current flowing through the drain resistor.

MOSFETs


Source degeneration3
Source Degeneration

(A)

Vgs

ids

iD

gmvgs

rds

Vg-ground

(input)

Vs-ground

  • Now lets look at the current flowing through the node marked (A)

  • To get vds, we need to get the voltage dropped across the source resistor. But the current flowing through the drain resistor is the same as flowing through the source resistor

MOSFETs


Source degeneration4
Source Degeneration

  • So back to the KCL equation.

  • Now at this point we could continue on including rDS, but let us make an assumption that in saturation, the small signal impedance of the device is much larger than either RD or RS, so we can assume the current contribution from the rds path is small, and that the above equation for iD can be simplified to

MOSFETs


Source degeneration5
Source Degeneration

  • Now to finalise the iD equation, we need to determine vgs, but we know from the circuit that

MOSFETs


Source degeneration6
Source Degeneration

  • Therefore to work out the final gain of the system, we get

  • The gain of this circuit is now much more resilient to changes in gm. However source degeneration is much less effective than emitter degeneration as gm is a small number and for it to be truly independent RSgm >> 1 and this requires a large RS, greater than 10k. This is not really practical as any decent gain would then require RD to be hundreds of k.

MOSFETs


Example18
Example

  • Given the following circuit construct the hybrid- small signal equivalent circuit without simplification. Assume a source-drain capacitance of 500 fF. Using this circuit, assume that the gate-drain capacitance can be ignored. With this simplified circuit, calculate the small signal voltage gain for this circuit at an operating frequency of 100kHz. You may assume that the biasing is such that the following parameters have been obtained. Defend any simplifications that you make.

  • VT = 1 V rds = 20 k

  • gm = 1.4 mA/V

  • 6k

    400k

    300k

    400

    MOSFETs


    Example19
    Example

    CS

    500

    Drain

    20k

    Gate

    6000

    400

    • The key thing is

      • that the source resistor separates the source from the ground.

      • that the drain resistor goes from drain to ground.

      • That the input goes from gate to ground and not gate to source.

      • That the capacitor connects gate and drain.

    MOSFETs


    Example20
    Example

    CS

    500

    Drain

    20k

    Gate

    6000

    400

    First let us examine the source capacitance. It is 1uF, at 100kHz, it presents an impedance of

    Compared to RS this is negligible, even if any current was to flow. So let’s discard this.

    MOSFETs


    Example21
    Example

    500

    Drain

    20k

    6000

    400

    The input is split over the gate, source and ground. So need to find what VS-ground is first.

    Let’s examine the currents at the drain, the current through the drain resistor is the same as that through the source resistor, so the difference between the voltage dropped across RD and RS is VDS

    MOSFETs


    Example22
    Example

    (A)

    500

    20k

    6000

    400

    Lets examine KCL at node (A)

    MOSFETs


    Example23
    Example

    (A)

    500

    20k

    6000

    400

    Now examining the input, the input is composed of two components, the gate-source voltage and also the source-ground component.

    MOSFETs


    Example24
    Example

    Now the standard expression for

    I could just plug the numbers in, so I will. Plugging the numbers in is possible at any time, my preference is to leave them later so I can see if the structure looks familiar.

    MOSFETs


    Example25
    Example

    Now the standard expression for

    MOSFETs


    Gate drain capacitance
    Gate-Drain Capacitance

    • Something we’ve touched upon before is the presence of capacitance in the models of both the MOSFET and the BJT.

    • These capacitances are the reason for the upper limitations on the high frequency performance of these systems.

    • However we never mathematically investigated these, and this is our opportunity to do so for the MOSFET common source amplifier.

    MOSFETs


    Gate drain capacitance1
    Gate-Drain Capacitance

    • Consider the following circuit

    • We’ll not consider source resistances in this analysis but we know how to handle it if it was necessary. An input resistance is required.

    MOSFETs


    Gate drain capacitance2
    Gate-Drain Capacitance

    • The DC bias analysis is not affected, the capacitors are ignored as infinite resistances, so the only change is in the small signal analysis.

    rds

    gmvgs

    MOSFETs


    Gate drain capacitance3
    Gate-Drain Capacitance

    • Capacitors make things more difficult so lets make some simplifications.

    • Bias resistors are large, so discard them.

    • Combine the two resistors, rds and RD into

    • one resistor RL

    gmvgs

    RL

    gmvgs

    MOSFETs


    Gate source capacitance
    Gate-Source Capacitance

    RL

    gmvgs

    • We will do this analysis in two stages, first we’ll only look at the capacitance across the gate-source, assuming the other capacitance didn’t exist.

    • From our previous analyses, we know for this configuration

    MOSFETs


    Gate source capacitance1
    Gate-Source Capacitance

    RL

    gmvgs

    • Now ignoring the transient, we can say the impedance of the capacitor is

    • This acts as a voltage divider with the resistor, vGS can be found from the voltage divider theorem

    MOSFETs


    Gate source capacitance2
    Gate- Source Capacitance

    • This formula indicates the voltage divider response for an RC circuit for a capacitor charging from zero.

    • For low frequencies, the capacitor charges fully, taking the full input voltage, =0, gives vgs=vinput. As the frequency goes up, the voltage across the capacitor doesn’t have time to fully charge, hence it doesn’t obtain the full value. As the frequency increases, the capacitor voltage is changing so fast it’s average value is near zero.

    MOSFETs


    Gate source capacitance3
    Gate- Source Capacitance

    • Now for a measure of the current into the gate,

    • The current is going to be very small, as gate capacitance is on the order of 10-13, so the current would only get to 1uA, if the frequency was over a few hundred megahertz.

    • However the structure of the result will be important in the next section.

    MOSFETs


    Gate source capacitance4
    Gate- Source Capacitance

    • The point at which the voltage is reduced by 1.414 (square-root of 2) is the power-equivalent of the 3dB point, the point where the power of that corresponding voltage is halved.

    • In this equation, it will be when vGS is 0.707vin

    MOSFETs


    Gate source capacitance5
    Gate- Source Capacitance

    • So when the frequency (in radians) reaches 1/RC then the power of the signal is halved. This will be important as we go on.

    MOSFETs


    Gate source capacitance6
    Gate- Source Capacitance

    • So back to voltage gain. If vgs is given above, we can now calculate the voltage gain of the system.

    MOSFETs


    Gate source capacitance7
    Gate- Source Capacitance

    • The voltage gain here is the same as before when the frequency ( =0). However as the frequency goes up, the gain goes down. Now this is the same form as before, so we can now quickly say, the gain of the circuit is limited by CGSat upper frequencies, and when

    • the power gain of the circuit is reduced to half of it’s maximum value, the voltage gain is reduced to 0.7071 times it’s maximum value.

    MOSFETs


    Gate source capacitance8
    Gate- Source Capacitance

    3dB point

    MOSFETs


    Gate drain capacitance4
    Gate-Drain Capacitance

    • So far, we’ve avoided the gate-drain capacitance. However this is the most important one but the maths is more complicated as the capacitance connects the gate and the drain.

    • The small signal model we’ll use is the following. We’ll ignore the gate-source capacitance, and the bias resistors, and the source resistance.

    RL

    gmvgs

    MOSFETs


    Gate drain capacitance5
    Gate-Drain Capacitance

    vgate-drain

    RL

    vGS

    gmvgs

    vDS

    • Due to the small signal current path from the input to the drain, we need to look at the gate current.

    MOSFETs


    Gate drain capacitance6
    Gate-Drain Capacitance

    vgate-drain

    igate

    iLoad(Drain)

    (A)

    RL

    vGS

    vDS

    gmvgs

    • Now lets look at the current flow into the node marked (A)

    • Now we have the output voltage in terms of the input voltage and the gate current.

    MOSFETs


    Gate drain capacitance7
    Gate-Drain Capacitance

    • But we still need to calculate igate

    • Normally we can say that jwCGDRL compared to one, so let’s drop the denominator

    MOSFETs


    Gate drain capacitance8
    Gate-Drain Capacitance

    • Ahh time to make a quick revision of the gate-source capacitance circuit analysis results.

    • There we noticed that Igate was equal to….

    • And our current here is

    • From our analysis we could make an assumption that the gate-drain capacitance is acting in a similar manner to a type of gate-source capacitance. It is however scaled by

    • 1+gmRL which can often be a very large number.

    • This would make the equivalent gate-source capacitor much larger.

    MOSFETs


    Gate drain capacitance9
    Gate-Drain Capacitance

    • This scaling effect on the gate-drain capacitor is called the MILLER EFFECT and it is extremely important in MOSFETs, though it was first noted in valves. A similar effect occurs with resistances thing that are viewed across a gain stage (remember the effective size of the emitter resistance in BJT circuits).

    • The gate-drain capacitance is smaller than the gate-source capacitance, but due to the Miller effect it is the dominant parasitic capacitance. The effect can be minimised through circuit design but it will generally be the dominant factor in limiting the circuits upper frequency.

    MOSFETs


    Gate drain capacitance10
    Gate-Drain Capacitance

    Now if we make an assumption that compared to the drain current the gate current is going to be very small, then we can separate out the two sides, and we’re back to the easier analysis.

    RL

    gmvgs

    MOSFETs


    Gate drain capacitance11
    Gate-Drain Capacitance

    Given this simpler circuit

    RL

    gmvgs

    So now we can quickly say that the gain of this system is given by

    And the 3dB point is now

    MOSFETs


    Example26
    Example

    • Given the following circuit construct the hybrid- small signal equivalent circuit without simplification. Assume a source-drain capacitance of 500 fF. Using this circuit, calculate the small signal voltage gain for this circuit at an operating frequency of 100kHz. Then recalculate the gain at 100 MHz. You may assume that the biasing is such that the following parameters have been obtained. Defend any simplifications that you make.

  • VT = 1 V rds = 20 k

  • gm = 1.4 mA/V

  • MOSFETs


    Example27
    Example

    RL

    rDS

    gmvgs

    • The key thing is

      • That the capacitor connects gate and drain.

      • The load resistor is in parallel with the rDS and connects from drain to ground.

    • The next step to do in the analyses is either combine the two capacitances together. The smaller one will dominate such that it will be negligible.

    MOSFETs


    Example28
    Example

    RL

    rDS

    gmvgs

    • There are two approaches to solving this problem.

    • You either know the Miller Capacitance and you can explain why and then defend your usage of it

    • or

    • You can just use basic circuit analysis to get the same result.

    • Either way is possible but the second way is a more secure route as it relies less on memory and more on basic principles.

    • For brevity, I am going to just use the Miller simplification.

    MOSFETs


    Example29
    Example

    RL

    gmvgs

    • vGS can be quickly calculated from a voltage divider approach.

    MOSFETs


    Example30
    Example

    • Thus the voltage gain can now we quickly calculated.

    MOSFETs


    Example31
    Example

    • Now lets get the magnitude of the gain value.

    • At 100kHz, =628.103 radians/s

    MOSFETs


    Example32
    Example

    • At 100MHz, =628.106 radians/s

    • It would not take much to vary this approach to

    • calculate the -3dB point of a circuit. It’s just a case of taking a low frequency point, say 100kHz, and finding the value of frequency such the power is halved.

    MOSFETs


    Source follower
    Source Follower

    A source follower circuit consists of a current source and a transistor.

    D

    Ibias

    G

    S

    S

    Ibias

    G

    D

    MOSFETs


    Source follower1
    Source Follower

    A source follower circuit is biased by a current being forced through it.

    Assuming the device is in saturation, then as S is floating, VGS will adjust itself so that the current IBIAS can flow.

    The current source can be implemented by a current mirror circuit.

    D

    G

    S

    Ibias

    MOSFETs


    Source follower2
    Source Follower

    The transistor must adapt to the current being forced through it. S is floating so that means that VGS is undefined even if G voltage is known. VGS will take a value such that the following equation is satisfied

    Now, here’s something worth noting

    D

    S

    G

    MOSFETs

    The transistor is always in saturation


    Hand waving explanation
    Hand Waving Explanation

    VGSis constant for a given input current. The source voltage will be lower than the gate by whatever voltage is required by the bias current. More current, a greater voltage drop.

    For a fixed current, VGS is fixed, so if the gate voltage drops, the source must drop by an equal amount. Similarly if it rises. The difference in the two is kept constant provided the bias current is constant.

    The source follows the gate input voltage exactly, except for a DC voltage drop which is determined by the bias current.

    D

    G

    S

    Ibias

    MOSFETs


    Small signal analysis
    Small Signal Analysis

    GATE

    gmvgs

    DRAIN

    rDS

    vGS

    SOURCE

    vinput

    vout

    First thing to note is that the output voltage is the voltage dropped across the SOURCE Resistor.

    Secondly the three resistors are in parallel as both the bottom of the source and load resistors and the top of the rDS(connected to drain) resistor are tied to AC signal ground. So they can all be added in parallel to make a combined resistor

    Finally the output voltage is a factor in the value of vgs so we have a connection between output and input which complicates things.

    MOSFETs


    Small signal analysis1
    Small Signal Analysis

    GATE

    gmvgs

    DRAIN

    rDS

    vGS

    SOURCE

    vinput

    vout

    Now all the gmvGS current will flow through the combined resistor so

    Note: there’s no minus sign so hence there’s no inversion. The output and input signals are in phase.

    MOSFETs


    Small signal analysis2
    Small Signal Analysis

    GATE

    gmvgs

    vGS

    SOURCE

    vinput

    Now to express the output voltage in terms of the input:

    MOSFETs


    Small signal analysis3
    Small Signal Analysis

    with

    the voltage gain of the system is easily found

    Normally Rtotal is designed to be very large, then gmRtotal is much larger than 1, so this simplifies to a small signal voltage gate of unity, one.

    The source follower has a signal gain which is very close to one and where the output DC voltage is a VGS voltage shift on the input signal DC voltage.

    MOSFETs


    Notes on the source follower
    Notes on the Source Follower

    • We did not consider the bulk-source effect. We do not have the bulk and source voltage at the same voltage. This is a minor effect but will cause a small reduction in small signal gain. It could be removed by setting the bulk and the source to the same voltage, but then care would need to taken to ensure that the system never enters a state where either the drain or gate would drop below the bulk voltage. Normally it is safe to tie bulk and source together.

    • This analysis is accurate for small signal swings. Large input signal swings will enter regions with different gm’s and hence we will get some distortion as the signal travels between regions.

    • This circuit is used very often as a level-shifter. To shift up, use a PMOS device, down requires NMOS. The magnitude of the shift is dependent on the bias current which we now know how to control through current mirrors.

    MOSFETs


    Output impedance of the source follower
    Output Impedance of the Source Follower

    • The main reason that the source-follower is used as an output stage is it’s low output impedance. We’ll now investigate this from the small signal analysis point of view.

    • To find the output impedance of a system, we set the input to zero and find the resulting output impedance, given an output voltage V.

    GATE

    DRAIN

    gmvgs

    rDS

    vGS

    SOURCE

    V

    • Something worth spotting is that VGS is equal to -Vout

    MOSFETs


    Output impedance of the source follower1
    Output Impedance of the Source Follower

    • Now all the components are in parallel, so let’s bring them together, simplifying the structure.

    • gmVgs is interesting as it becomes

    rds

    Rsource

    gmvgs

    • The - sign indicates that the current flows down, so for a positive Vout, the current flows from top to bottom. But the current defined by gmVout corresponds to the current that would be produced by a resistance of

    • So we get the following circuit diagram.

    rds

    Rsource

    1/gm

    MOSFETs


    Output impedance of the source follower2
    Output Impedance of the Source Follower

    rds

    Rsource

    1/gm

    • The output impedance of this combination is given by

    • Now rDS is large in a MOSFET, and Rsource is designed to be large for good signal following but 1/gm corresponds to a small number, in the order of hundreds of ohms.

    • So rout can be simplified to

    • When you need an output of an amplifier to have low output impedance, for example driving large capacitors or a high resistance, you use a source follower circuit to provide the low output impedance while not affecting the signal itself in anyway.

    MOSFETs


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