MOSFETs. Metal Oxide Semiconductor Transistors ( MOSFETs ). Recommended Book: Sedra & Smith, Microelectronics, 4 th Edition Boylestad & Nashelsky, Electronic Devices …, 8 th Edition. Johns & Martin Analog Integrated Circuit Design. FET Notation. PMOS (N channel bulk). S. B. S.
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Recommended Book:
Sedra & Smith,
Microelectronics, 4th Edition
Boylestad & Nashelsky,
Electronic Devices …, 8th Edition.
Johns & Martin
Analog Integrated Circuit Design
MOSFETs
S
B
S
P
N
P
G
G
B
D
D
Arrow on
the Source
The FET is a
4 terminal device
B
D
D
N
P
N
G
G
B
S
S
MOSFETs
W
L
MOSFETs
B
D
D
ID
N
P
N
G
G
S
S
MOSFETs
MOSFETs
VGS
NMOS
GATE
Metal
IS
ID
N
N
P
Bulk
Source
Drain
MOSFETs
VGS
NMOS
GATE
Metal
IS
ID
N
N
P
Bulk
Source
Drain
MOSFETs
NMOS
GATE
Metal
Insulator
Semiconductor
MOSFETs
VGS
NMOS
GATE
Metal
IS
ID
N
N
P
Bulk
Source
Drain
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
VGSVT
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
Metal
Source
Drain
N
N
L’
L
MOSFETs
Metal
Source
Drain
N
N
VDS(sat)=VGSVT
L’
L
VDS VDS(sat)
MOSFETs
Metal
Source
Drain
N
N
L’
L
MOSFETs
Metal
Source
Drain
N
N
L’
L
MOSFETs
Metal
Source
Drain
N
N
L’
L
MOSFETs
is always positive
MOSFETs
Bigger VA the better.
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
iG
iD
Gate
Drain
+
vGS

+
vDS

gmvGS
rds
Source
MOSFETs
MOSFETs
Same gm as in the
saturated region when
VDS reaches saturation.
MOSFETs
MOSFETs
Increase the gate voltage, you
linearily increase the gain.
Increase the drain current, you
increase the gain by only a
squareroot factor.
Note:
MOSFETs
MOSFETs
If is small, and it is normally so, then rds is the reciprocal of a small current by a very small number, resulting in a very large small signal resistance.
MOSFETs
MOSFETs
MOSFETs
Looking at the two values for rds we can compare their respective values
Assume =1 for a moment, and assume VOD=1 as well, then the saturation value is just twice that of the triode resistance.
If VOD is less than one, the saturation resistance is larger again due to the inversion effect. If VOD larger then the saturation resistance is smaller.
MOSFETs
However let’s consider a real circuit,
This means that assume VOD = 1 (for simplicity) then the small signal saturation region resistance can be significantly greater, often 100 times greater than in the triode region.
MOSFETs
MOSFETs
The DC current for small voltages in the triode region is given below
Given this, it is possible to work out what the DC resistance RDS would be
MOSFETs
MOSFETs
Let’s consider the on resistance for DC current just at pinchoff. At pinchoff, the current is given as
But it should be noted that
Thus
Twice RDS(triode)
MOSFETs
In saturation, the current increases only a little with increase VDS, (assuming channel modulation) so this means that the drainsource resistance is going to rise.
The current in the saturation region is given by
Thus
MOSFETs
If we look at the circled term, when VDS=VOD then this RDS is the same as that at pinchoff.
As VDS increases however the circled term increases linearly, indicating an increase in device resistance.
The other term is due to channel modulation and it allows additional current to flow and it effectively reduces the resistance a little but it is the weaker of the two terms.
But remember, this is still a small resistance as the currents can be quite large for some selections of VOD and VDS.
MOSFETs
MOSFETs
Calculate the effective resistance between source and drain for a N channel MOSFET transistor with the following characteristics
VDS = 0.1 V
VT = 1.0 V
VGS = 5.0 V
nCox = 0.2 mA/V2
W = 5.0 m
L = 0.25 m
= 0.01
Calculate the effective DC and small signal resistance if VDS was increased to 6 V.
MOSFETs
Now from the equation we need to find RDS(pinch) but we know it’s twice RDS(triode) for the same VOD.
Now ID(pinch)
MOSFETs
Large DC signal MOSFET applications are very important. In reality they are some of the most important circuits in electronics.
The main characteristic that you need to remember is that the MOSFET is a very good switch.
When the device is FULLY ON, ie the VGS is at its maximum value, the onresistance of the circuit, both AC and DC is relatively low.
When the device is FULLY OFF, VGS is at its minimum value, the on resistance of the circuit, again AC and DC is near infinite. (No inversion channel, no conduction).
The main switching circuits that you’ll encounter are transmission gates and logic gates.
MOSFETs
To turn a MOSFET fully off, you want to remove ANY inversion region that may exist.
A strong inversion region occurs when the gatechannel voltage exceeds the threshold voltage.
Assuming NMOS
However a weak inversion channel can occur below this.
To ensure that there is no channel, set the gate voltage to the lowest available voltage, less than or equal to the source and bulk voltages. (Note source voltage has to be greater than bulk). This guarantees that no charge is attracted to the gate, no chance of an inversion region.
Assuming NMOS
MOSFETs
To turn a MOSFET fully on, you want to maximise the inversion region. This occurs when the gatechannel voltage is at it’s maximum possible value (Assuming NMOS).
A strong inversion region occurs when the gatechannel voltage exceeds the threshold voltage.
Thus the maximum VOD will ensure the minimum RDS (and coincidentally rds).
MOSFETs
Control 1
Signal 1
Control 2
Signal 2
Output
Control 3
Signal 3
In analog circuitry it is always very useful to be able to disconnect signals and reconnect them.
For example the multiplexor
MOSFETs
Control 1
Signal 1
Control 2
Signal 2
Output
Control 3
Signal 3
In a digital system, you could use AND gates to control the multiplexor. If you ANDed your signals with your control signals, the input would only get to the output IF the control signal was set to 1.
However in practice you’d need to do a few other things first because you can’t have an output of a 1 and 0 on the same wire. The principle is okay though.
MOSFETs
In the analog world, the input signals are continuous in value, or in simple terms, they may take any value in the range available.
So if the range was 0 to 1, they may take 0.44554 or 0.7. All are equally valid. Therefore LOGIC type switches are not acceptable.
What we need to aim for is a physical representative of the ideal switch.
MOSFETs
Zero Resistance
Infinite Resistance
Zero / Low / Infinite
Zero / Low / Infinite
Zero / Low / Infinite
Zero / Low / Infinite
MOSFETs
Now a single transistor switch can be very useful. Quite often they are used in powerdown circuits or to turn off sections of a circuit.
Powerdown circuits work by setting the gates of transistors to their FULLY OFF values. This means that any amplification or transistor action is turned off.
The switch is placed between the gate and ground (NMOS) or VDD (PMOS).
This does mean that there is a low resistance path to ground/VDD which if not designed for could lead to large currents feeding back to the source of the input signal.
MOSFETs
PMOS’s are best used to pull signals to the high voltage rail.
NMOS’s are best used to pull signals to the low voltage rail.
Note: The same powerdown signal could not be used to control both transistors.
MOSFETs
Single transistor switches can be also be used inline to disconnect a signal.
Note bulk tied
to ground.
However the problem then is that there is now a section of wire that is floating. We don’t know what voltage it is?
This is very bad as parasitic capacitances, CGS, CGD, may charge up, turning the NMOS’s on, or even blowing transistors (pumping effect).
MOSFETs
The solution to this is to ensure some other circuit element controls the voltage at this node.
In a powerdown circuit, we could add the powerdown transistor. Then the inline transistor protects the input from any current flow to the ground or from the positive supply.
In a multiplexor, one other gate should always be selected, a default one if necessary and this would control the voltage on the wire at the source side of the inline transistor.
The following two pages have a powerdown circuit and a multiplexor.
MOSFETs
MOSFETs
We need to look at the inline transistor in a little more detail.
NMOS
Gate
VGS
Source
Drain
VSB
Bulk
When this is fully on, we want it to present little resistance to the signal. So what we need to ensure is that VGS>VT and that the source voltage is always greater than the bulk
MOSFETs
Gate
VGS
Source
Drain
VSB
Bulk
Okay.. The first thing to do is wire the bulk to ground. This ensures that the SourceBulk PN junctions remains reverse biased.
The second thing we need to do is consider the range of voltages that the signal on the source can experience.
MOSFETs
Imagine that we are turning this gate on, so VG=5V. Let’s assume it’s a 05 V system, the signal can go from 05V and that the VT of our transistor is 2.5 V.
So the critical voltage to watch is VGS. This is
MOSFETs
Now what this chart would indicate is that the impedance of the transistor is small when Vsignal is small. This is because
VGS = 5  Vsignal > VT (1V)
But if Vsignal increases, then VGS decreases and the impedance slowly rises and then shoots up in subthreshold and hits infinity when there is insufficent VGS for an inversion region.
MOSFETs
So basically if the input goes too high, the transistor will begin to turn off even when we have the gate voltage at it’s maximum value.
This puts an upper limit on the maximum value for the input signal for which this transistor is an acceptable switch.
However we never want to waste voltage range like this. Reducing the allowed voltage range, reduces our maximum SNR (signaltonoise ratio).
A solution to this problem is to use a second transistor.
MOSFETs
Note: Sources
connected.
This circuit consists of a PMOS and an NMOS. The inverter is present to change the control signal from a 5 to a 0 (logic 1 to 0) and visaversa.
This is needed because to turn a PMOS on, we need VG=0 (remember opposite way) and for the NMOS on, VG=5.
MOSFETs
The transistors can be modeled as variable resistors, and they are in parallel.
MOSFETs
Control Voltage = 5V
PMOS
NMOS
Combined
Now we know that when the signal when high, the NMOS was high impedance. However the PMOS has the opposite effect. It requires the signal (source) to be higher than the gate (which is now 0V) and so it shows a low impedance.
The parallel combination ensures that irrespective of the signal value, the impedance when the transistors are turned ON is very LOW.
MOSFETs
The standard symbol for the transmission gate is
Indicates Inverted
signal for PMOS
When drawn like this, when the control signal goes high, the gate is closed (LOW resistance). High gate voltage, low resistance. Low gate voltage, infinite resistance.
Note: The symbol is symmetric. Remember the structure of the MOSFET, there is no difference between source and drain so generally you can wire this anyway you like, input on either side.
MOSFETs
MOSFETs
MOSFETs
Design a switch capable of being driven by a 0/2.5V logic signal that can switch an input signal that ranges from 0.3 to 2.2 V. The effective resistance of the switch when open should exceed 100 M and when closed should present no more than 25.
PMOS NMOS
VT = 0.8 V VT = 0.8 V
mpCox = 30 mA/V2mpCox = 90 mA/V2
lp = 0.05 lp = 0.05
Minimum device length = 0.18um
MOSFETs
First: The voltage range of the input is such that it goes below 0+VT for the NMOS and 2.5VT for the PMOS. So a single transistor switch would be unsuitable for the task. The transistor would be turned off by the input signal. Therefore you must use a transmission gate.
Second: the offresistance of a transmission gate is the parallel resistance of two devices with no inversion region, hence two reverse bias diodes. It’s going to be big.. So let’s say the off condition has been satisfied.
MOSFETs
MOSFETs
Pick the extreme, from the equation, the PMOS will have the bigger resistance due to the smaller mobility (mCox = 30mA/V). So if we satisfy the PMOSon extreme, then the NMOSon side will be satisfactory too.
Now at the extreme, Vsignal=0, VG=2.5, VT=0.8 so
Therefore
MOSFETs
Pick the centre, here we need to calculate both the NMOS and the PMOS transistor resistances.
In the centre, Vsignal = 1.25, so
For this example, it just happens to be the same for P and N.
Therefore
MOSFETs
So now we have two constraints for us to satisfy our maximum resistance requirements.
Centre
PMOS extreme
So the PMOS extreme is the tougher one, so set W/L to be 1000, safe enough.
Use minimum length for L, giving
This is a BIG device.
Finally, we did not factor in temperature or variations in process (mobility), which would require us to make the device even bigger and test more extremes or corners.
MOSFETs
Before we look at circuits, there’s a couple of points worth clarifying at this point.
The transistors in the following circuits can be considered as SWITCHES once they have changed state.
For the moment we shall not worry about what happens when they are changing state.
There will be no floating nodes anywhere in these circuits.
MOSFETs
In the inverter, the NMOS source is tied to ground, the PMOS source is tied to VDD. So when we gave a gate voltage, there is no issue of what VGS is.
MOSFETs
100 M
10 k
Consider a logic 1 input (high voltage).
PMOS VGS = 0, PMOS is OFF
high resistance
NMOS VGS = VDD, NMOS is ON
low resistance
Voltage divider theorem says that the output voltage is going to be effectively zero (Logic 0)
MOSFETs
10 k
100 M
Consider a logic 0 input (low voltage).
PMOS VGS = VDD, PMOS is ON
low resistance
NMOS VGS = 0, NMOS is OFF
high resistance
Voltage divider theorem says that the output voltage is going to be effectively VDD (Logic 1)
MOSFETs
Now consider it when we have set a value on our input, either high or low. What is the current flowing through the two transistors?
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
Input
Output
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
Source (PMOS)
Sink (NMOS)
MOSFETs
Input
Current
Reproduced
Current
D
G
S
MOSFETs
Input
Current
MOSFETs
Input
Current
MOSFETs
MOSFETs
Input
Current
Iin
Iout
Reproduced
Current
Iin=Iout
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MOSFETs
MOSFETs
MOSFETs
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MOSFETs
MOSFETs
MOSFETs
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MOSFETs
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MOSFETs
MOSFETs
rds
gmvgs
MOSFETs
rds
gmvgs
MOSFETs
id
rds
gmvgs
MOSFETs
id
rds
gmvgs
MOSFETs
MOSFETs
MOSFETs
Vgs
gmvgs
rds
Vgground
(input)
Vsground
MOSFETs
Vgs
ids
iD
gmvgs
rds
Vgground
(input)
Vsground
MOSFETs
(A)
Vgs
ids
iD
gmvgs
rds
Vgground
(input)
Vsground
MOSFETs
MOSFETs
MOSFETs
MOSFETs
6k
400k
300k
400
MOSFETs
CS
500
Drain
20k
Gate
6000
400
MOSFETs
CS
500
Drain
20k
Gate
6000
400
First let us examine the source capacitance. It is 1uF, at 100kHz, it presents an impedance of
Compared to RS this is negligible, even if any current was to flow. So let’s discard this.
MOSFETs
500
Drain
20k
6000
400
The input is split over the gate, source and ground. So need to find what VSground is first.
Let’s examine the currents at the drain, the current through the drain resistor is the same as that through the source resistor, so the difference between the voltage dropped across RD and RS is VDS
MOSFETs
(A)
500
20k
6000
400
Now examining the input, the input is composed of two components, the gatesource voltage and also the sourceground component.
MOSFETs
Now the standard expression for
I could just plug the numbers in, so I will. Plugging the numbers in is possible at any time, my preference is to leave them later so I can see if the structure looks familiar.
MOSFETs
MOSFETs
MOSFETs
rds
gmvgs
MOSFETs
gmvgs
RL
gmvgs
MOSFETs
RL
gmvgs
MOSFETs
RL
gmvgs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
RL
gmvgs
MOSFETs
vgatedrain
RL
vGS
gmvgs
vDS
MOSFETs
vgatedrain
igate
iLoad(Drain)
(A)
RL
vGS
vDS
gmvgs
MOSFETs
MOSFETs
MOSFETs
MOSFETs
Now if we make an assumption that compared to the drain current the gate current is going to be very small, then we can separate out the two sides, and we’re back to the easier analysis.
RL
gmvgs
MOSFETs
Given this simpler circuit
RL
gmvgs
So now we can quickly say that the gain of this system is given by
And the 3dB point is now
MOSFETs
MOSFETs
RL
rDS
gmvgs
MOSFETs
RL
rDS
gmvgs
MOSFETs
MOSFETs
A source follower circuit consists of a current source and a transistor.
D
Ibias
G
S
S
Ibias
G
D
MOSFETs
A source follower circuit is biased by a current being forced through it.
Assuming the device is in saturation, then as S is floating, VGS will adjust itself so that the current IBIAS can flow.
The current source can be implemented by a current mirror circuit.
D
G
S
Ibias
MOSFETs
The transistor must adapt to the current being forced through it. S is floating so that means that VGS is undefined even if G voltage is known. VGS will take a value such that the following equation is satisfied
Now, here’s something worth noting
D
S
G
MOSFETs
The transistor is always in saturation
VGSis constant for a given input current. The source voltage will be lower than the gate by whatever voltage is required by the bias current. More current, a greater voltage drop.
For a fixed current, VGS is fixed, so if the gate voltage drops, the source must drop by an equal amount. Similarly if it rises. The difference in the two is kept constant provided the bias current is constant.
The source follows the gate input voltage exactly, except for a DC voltage drop which is determined by the bias current.
D
G
S
Ibias
MOSFETs
GATE
gmvgs
DRAIN
rDS
vGS
SOURCE
vinput
vout
First thing to note is that the output voltage is the voltage dropped across the SOURCE Resistor.
Secondly the three resistors are in parallel as both the bottom of the source and load resistors and the top of the rDS(connected to drain) resistor are tied to AC signal ground. So they can all be added in parallel to make a combined resistor
Finally the output voltage is a factor in the value of vgs so we have a connection between output and input which complicates things.
MOSFETs
GATE
gmvgs
DRAIN
rDS
vGS
SOURCE
vinput
vout
Now all the gmvGS current will flow through the combined resistor so
Note: there’s no minus sign so hence there’s no inversion. The output and input signals are in phase.
MOSFETs
GATE
gmvgs
vGS
SOURCE
vinput
Now to express the output voltage in terms of the input:
MOSFETs
with
the voltage gain of the system is easily found
Normally Rtotal is designed to be very large, then gmRtotal is much larger than 1, so this simplifies to a small signal voltage gate of unity, one.
The source follower has a signal gain which is very close to one and where the output DC voltage is a VGS voltage shift on the input signal DC voltage.
MOSFETs
MOSFETs
GATE
DRAIN
gmvgs
rDS
vGS
SOURCE
V
MOSFETs
rds
Rsource
gmvgs
rds
Rsource
1/gm
MOSFETs
rds
Rsource
1/gm
MOSFETs