Impact of Doping Concentration Gradient and Spacer Thickness on Device Performance of UTB-SOI CMOS

1. Impact of Doping Concentration Gradient and Spacer Thickness on Device Performance of UTB-SOI CMOS Hannes Luyken CPR ND Session 1.1: Transistor architecture and fabrication T. Schulz, C. Pacha, R. J. Luyken, M. Städele, J. Hartwich, L. Dreeskornfeld, E. Landgraf, J. Kretz, W. Rösner, M. Specht, F. Hofmann and L. Risch Infineon Technologies AG, Corporate Research Nano Devices, Otto-Hahn-Ring 6, D-81730 Munich, Germany ULIS 2003 Ultimate Integration of Silicon N e v e r s t o p t h i n k i n g .

2. Outline • Motivation for the ultra thin body (UTB)-SOI device concept • Simulation method • Impact of technology parameters on device performance - source/drain doping concentration gradient - sidewall spacer thickness - silicon thickness - supply voltages • Conclusions

3. Motivation for the ultra thin body (UTB)-SOI device conceptwith undoped channel region • Undoped channel region ÜIncrease in drive current • New gate materials ÜVth adjustment

4. Simulation method • green area: interconnects and wiring and geometrical aspects of gates • blue area: intrinsic device and substrate material • red area: Äcoupled device and circuit simulation

5. Device structure and technological parameters • No additional source/drain series resistances were chosen • NMOS and PMOS have the same structure apart from the different doping sequence

6. Simulation scheme and circuit structure • 2 Inverter 4 MOSFETs (n1, p1, n2, p2) • Additional R and C RC-load C-wiring • Input pulse (1ps) Delay between VOUT_1 and VOUT_2

7. Transient and transfer characteristic

8. Impact of technology parameters on inverter delay - source/drain doping gradient @ constant spacer

9. Impact of technology parameters on inverter delay - source/drain doping gradient @ constant spacer • Where is the effective / metallurgical channel length ? • Leff as figure of merit vanish

10. Impact of technology parameters on inverter delay - source/drain doping gradient @ constant spacer • Where is the effective / metallurgical channel length ? • Leff as figure of merit vanish • Is a relaxed doping gradient of 10 nm / decade sufficient ?

11. IOFF and ION versus doping gradient @ constant spacer • Steep doping profiles Ü suppress short channel effects

12. IOFF and ION versus doping gradient @ constant spacer • Steep doping profiles Ü suppress short channel effects • Shallow doping profiles Ü flood the channel with dopants • In most cases spacer thickness of 10nm is too thin

13. Impact of technology parameters on inverter delay - sidewall spacer thickness @ constant gradient

14. Impact of technology parameters on inverter delay - sidewall spacer thickness @ constant gradient • What is the optimal spacer thickness ?

15. Impact of technology parameters on inverter delay - sidewall spacer thickness @ constant gradient • What is the optimal spacer thickness ? • Thinner sidewall spacer Ü increase short channel effects • Thicker sidewall spacer Ü increase inverter delay

16. IOFF and ION vs. spacer thickness @ constant gradient • Thin spacer Ü leakage current increase

17. IOFF and ION vs. spacer thickness @ constant gradient • Thin spacer Ü leakage current increase • Thick spacer Ü drive current decrease • Best case for L=50nm LOP device is 20-25nm spacer thickness

18. Comparison with (bulk) roadmap trend:sidewall spacer thickness correlate with doping gradient • State of the art: 50nm spacer thickness, 5nm/decade abruptness

19. Impact of technology parameters on inverter delay - combination of spacer thickness and doping gradient

20. Impact of technology parameters on inverter delay - combination of spacer thickness and doping gradient

21. Impact of technology parameters on inverter delay - combination of spacer thickness and doping gradient • Compensation of spacer thickness and doping gradient • New figure of merit: doping concentration @ gate corner

22. IOFF and ION versus different spacer / doping gradient • HP-device and LOP-device specs achievable • IOFF spec for the LSTP-device demand thicker spacer

23. IOFF and ION versus different spacer / doping gradient • HP-device and LOP-device specs achievable • IOFF spec for the LSTP-device demand thicker spacer • For the presented doping profiles 10 nm/decade is the better choice

24. Transfer and output characteristicsfor different spacer thickness and doping gradient • Figure of merit: doping concentration 1E19cm-3 @ gate corner • Devices with different doping profiles but same driver performance • Increase of GIDL-current due to steeper doping concentration gradient

25. Conclusions • Doping concentration gradient and spacer thickness can compensate each other as design parameter. • Source/Drain doping concentration at the gate corner is an accurate figure of merit instead of Leff. • With a steeper doping concentration gradient there is no influence on the driver performance but a significant off-current due to the increase of the GIDL-current occurs. • HP- and LOP-devices can meet the roadmap targets but LSTP-devices are much harder to implement.

26. Back up

27. Subthreshold and output characteristics

28. Impact of sidewall spacer thickness in combination with doping gradient • figure of merit: doping concentration @ gate corner = 1E18cm-3

29. Impact of sidewall spacer thickness in combination with doping gradient • figure of merit: doping concentration @ gate corner = 1E18cm-3 • compensation of spacer thickness and doping gradient depends also from the source / drain doping concentration level (here 1E20cm-3)

30. Silicon film thickness replace doping concentration as figure of merit • Bulk: • SOI: • DG:

31. Gate delay metric (ITRS 2001)

32. Transit frequency (ITRS 2001)