CPUs

1. CPUs Caches

2. Cache operation • Many main memory locations are mapped onto one cache entry • May have caches for • instructions • data • data + instructions (unified) • Memory access time is no longer deterministic

3. Cache performance benefits • Keep frequently-accessed locations in fast cache • Temporal locality • Cache retrieves more than one word at a time • Sequential accesses are faster after first access • Spatial locality

4. Terms • Cache hit: required location is in cache • Cache miss: required location is not in cache • Working set: set of locations used by program in a time interval

5. Types of misses (3-C) • Compulsory (cold): location has never been accessed • Capacity: working set is too large • Conflict: multiple locations in working set map to same cache entry

6. Memory system performance • h = cache hit rate • tcache = cache access time, tmain = main memory access time • Average memory access time: • tav = htcache + (1-h)tmain

7. Multiple levels of cache L2 cache CPU L1 cache

8. Multi-level cache access time • h1 = cache hit rate • h2 = rate for miss on L1, hit on L2 • Average memory access time: • tav = h1tL1 + (h2-h1)tL2 + (1- h2-h1)tmain

9. Cache organizations • Set-associativity • Fully-associative: any memory location can be stored anywhere in the cache (almost never implemented) • Direct-mapped: each memory location maps onto exactly one cache entry • N-way set-associative: each memory location can go into one of n sets

10. Cache organizations, cont’d • Cache size • line (or block) size

11. Types of caches • Unified or separate caches • Write operations • Write-through: immediately copy write to main memory • Write-back: write to main memory only when location is removed from cache

12. Types of caches, cont’d • Cache block allocation • Read-allocation • Write-allocation • Access address • Physical address • Virtual address • Advantage: fast • Problems: context switching, synonyms or aliases

13. Replacement policies • Replacement policy: strategy for choosing which cache entry to throw out to make room for a new memory location • Two popular strategies: • Random • Least-recently used (LRU) • Pseudo-LRU

14. 1 0xabcd byte byte byte ... byte Direct-mapped cache valid tag data cache block tag index offset = value hit

15. Direct-mapped cache locations • Many locations map onto the same cache block • Conflict misses are easy to generate • Array a[] uses locations 0, 1, 2, … • Array b[] uses locations 1024, 1025, 1026, … • Operation a[i] + b[i] generates conflict misses

16. Set-associative cache • A set of direct-mapped caches: Set 1 Set 2 Set n ... hit data

17. Example: direct-mapped vs. set-associative

18. After 001 access: block tag data 00 - - 01 0 1111 10 - - 11 - - After 010 access: block tag data 00 - - 01 0 1111 10 0 0000 11 - - Direct-mapped cache behavior

19. After 011 access: block tag data 00 - - 01 0 1111 10 0 0000 11 0 0110 After 100 access: block tag data 00 1 1000 01 0 1111 10 0 0000 11 0 0110 Direct-mapped cache behavior, cont’d.

20. After 101 access: block tag data 00 1 1000 01 1 0001 10 0 0000 11 0 0110 After 111 access: block tag data 00 1 1000 01 1 0001 10 0 0000 11 1 0100 Direct-mapped cache behavior, cont’d.

21. 2-way set-associtive cache behavior • Final state of cache (twice as big as direct-mapped): set blk 0 tag blk 0 data blk 1 tag blk 1 data 00 1 1000 - - 01 0 1111 1 0001 10 0 0000 - - 11 0 0110 1 0100

22. 2-way set-associative cache behavior • Final state of cache (same size as direct-mapped): set blk 0 tag blk 0 data blk 1 tag blk 1 data 0 01 0000 10 1000 1 10 0111 11 0100

23. ARM Caches and write buffers

24. Caches and write buffers • Caches • Physical address • Virtual address • Memory coherence problem • Write buffers • To optimize stores to main memory • Physical address • Virtual address • Memory coherence problem

25. CP15 register 0 S=0 : unified cache S=1 : separate caches

26. CP15 register 0, cont’d

27. CP15 register 1 • C(bit[2]) : • 0=cache disabled, 1=cache enabled • W(bit[3]): • 0=wirte buffer disabled, 1=enabled • I(bit[12]): if separate caches are used, • 0=disabled, 1=enabled

28. CP15 register 7 • Write-only register which is used to control caches and write buffers • Clean • Invalidate • Prefetch • Drain write buffer

29. Example • StrongARM: • 16 Kbyte, 32-way, 32-byte block instruction cache • 16 Kbyte, 32-way, 32-byte block data cache (write-back)

30. MPC 850 Instruction and Data caches

31. Overview • Separate, 2-way, 2KB I-cache and 1KB D-cache • LRU replacement policy • Physical address • 16-byte cache blocks • Data cache states • Modified-valid • Unmodified-valid • Invalid • Instruction cache states: valid, invalid

32. Overview, cont’d • Both caches: disabled, invalidated, or locked • Individual cache blocks can be locked

33. Instruction cache organization

34. Data cache organization

35. Cache control registers • IC_CST

36. IC_CST

37. I-cache address register,I-cache data port register

38. Reading Data and Tags in the I-cache

39. User-level cache instructions – VEA • dcbt : data cache block touch – the byte addressed by EA is fetched into the data cache • dcbtst: data cache block touch for store • icbi : Instruction Cache block invalidate • dcbi: data cache block invalidate (OEA)

40. Memory coherence • Data cache to memory (DMA, Multiprocessor) • Snooping • Uncachable region • By SW • MPC 850 does not support snooping • Data cache to Instruction cache • Snooping • By SW