A Survey on HW/SW Codesign Representation Models Final Report

1. A Survey on HW/SW Codesign Representation ModelsFinal Report R91943084 R92943088

2. Outline • Introduction • Related Work&Objective • Representation • Comparison • Conclusion

3. Introduction • Modeling is a very important issue • Capture the features of system & describe • The system design process that combines the HW/SW perspectives from the earliest stages to exploit design flexibility and efficient allocation of functions • High-performance & low-cost productions • The increase in system complexity and the reduction in design times

4. Outline • Introduction • Related Work&Objective • Representation • Comparison • Conclusion

5. Related Work & Objective • The main purpose of goal is to explore the field of heterogeneous systems. • Many computational models have been proposed to represent digital systems. • Encompass a broad range of styles , characteristics and application domains. • Hardware description languages, namely VHDL, HardwareC, SDL, Statecharts…

6. Outline • Introduction • Related Work& Objective • Representation • Comparison • Conclusion

7. Representation Models • A variety of models has been developed and used to represent heterogeneous system • In the following we present the main representation models that have been utilized in codesign • Reactive & synchronous

8. Finite State Machines • The classical FSM representation is the most well-know model for describing control systems • Consists of a set of states, a set of inputs, a set of outputs, a function which defines the outputs in terms of inputs and states and a next-state function.

9. Disadvantages • The exponential growth of the number of the states as the system complexity rises! • No hierarchical constructions are allowed • In consequence FSMs are not appropriate for modeling practical systems.

10. Other Models • Discrete-Event system • The principal disadvantage of discrete-event modeling is its cost • Petri Nets • Four basic elements: • A set of places • A set of transitions • An input function that maps transitions to places • An output function

11. Other Models • Dataflow Graphs • Dataflow process networks is a model of computation to be used in signal processing systems. • Special cases: • SDF • CSDF • Communicating Processes • Synchronous/Reactive Models

12. Comparison of Models

13. Conclusions • Most of them are well suited for data or control-oriented systems but few representation support widely both. • Timing is an important subject in modern electronic systems, many of the related models do not have an explicit notion of time.

14. A Implementation Work based on Intel 8088 microprocessor with FSM

15. Intel 8088 Architecture

16. Control Unit Modeling

17. Control Unit Modeling • Feed : An interface between instruction queue and instruction decoder. It fetches instruction one by one and is controlled by instruction decoder because of unequal length of instruction. • Control : Decoding the instructions from memory and translating them into equal length instructions and puts data and address to register “Memreg. • Memreg contains EX, Reg_s, Reg_d1, Reg_d2, memaddr, data1 and data2 • Instruction decoder : Decoding the first one or two instruction and deciding the length of instructions. It fills the field in Reg_s, Reg_d1and Reg_d2. • Distributor : Analyzing and placing the instructions into Memaddr, data1 and data2.

18. EX register • (10-8) bits • move type (000) • logic/arithmetic type (001) • jump type (010) • call/return type (100) • (7-5) from where to where • reg->reg (000) • reg->ram (001) • data(in instruction)->reg(010) • data->ram(011) • ram->reg(100) • data->two reg(101) • default(111)

19. EX register • (4-1)operation(arithmetic and logic type) • add(0000) inc (0001) • sub(0010) mul (0011) • inv(0100) and (0101) • or(0110) xor (0111) • shift L(1000) shift R(1001) • rotate L(1010) rotate R(1011) • (4-1)operation(jump) • jump short (0000) • Direct within seg (0001) • Indirect within segment (0010) • Direct inter-segment (0100) • Jump on zero /on equal (1000) • (0) jump • from ram (1) • (0) word • word (1) • byte (0)

20. Modeling of the EX register with FSM

21. Modeling of the EX register with FSM if(EX[10:8]==3'b0)begin casex(move) 4'b0: begin //initial of move casex(EX[7:5]) 3'b00x,3'b10,3'b011: move<=4'b1; default: move<=4'b101; endcase end 4'b1: begin //read form register if(EX[7:5]==3'b10 | EX[7:5]==3'b11) sel_r<=3'b1; else if(~reg_s[3])begin//from gen_reg sel_go<=2'b0; addr_gen<=reg_s[2:0]; …………………………………… …………………………………… move<=4'b10; end 4'b10: begin enable<=1'b1; move<=4'b11; end ……………………………………. ……………………………………

22. Arithmetic Logic Unit

23. General Register • Data_in: A 16-bit bus for data to come in. • Data_out: A 16-bit bus to send out data. • Which: a 3-bit signal to indicate which register should be accessed. • Word : used to specify the data length comes in (or goes out) is a byte(8 bits) or a word(16 bits). • 8bits registers: AH, AL, BH, BL, CH, CL, DH, DL • 16 bits registers: AX, BX, CX, DX, IP, SP, BP, SI, DI

24. Simulation Result • MOVE ( immediate to Reg) • Instruction: 1100_0111_1100_0010_1000_1011_1001_0100 (c7c28b94) • Action: DX <= Data

25. Simulation Result • MOVE ( Reg to Reg) • Instruction: 1000_1011_1100_1010 (8bca) • Action: CX <= DX

26. Simulation Result • Step. 16 SUB (Reg to Reg) • Instruction: 0010_1011_1101_0001 (2bd1) • Action: DX = DX – CX

27. Reference • “Microcomputer Systems: The 8086/8088 Family Architecture, Programming, and Design,” Yu-Cheng Liu, Glenn A. Gibson. • “UML-Based Co-Design for Run-Time Recon-gurable Architectures,”Thomas Beierlein, Dominik FrÄohlich, Bernd Steinbach. • “A Model-Based Approach to System-Level Co-Design,”Thomas Beierlein, Dominik FrÄohlich, Bernd Steinbach. • “A Survey on Hardware/Software Codesign Representation Models,” Luis Alejandro Cortés, Petru Eles and Zebo Peng.