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SIFT UPGRADE. Marvin Johnson. Background. SVX 2 readout choice wanted common readout electronics Charge signal was roughly comparable to silicon SVX 3 development precluded new SVX chip Chip was “free” SIFT development UC Davis project Subcontracted to commercial firm

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sift upgrade

SIFT UPGRADE

Marvin Johnson

background
Background
  • SVX 2 readout choice
    • wanted common readout electronics
    • Charge signal was roughly comparable to silicon
    • SVX 3 development precluded new SVX chip
    • Chip was “free”
  • SIFT development
    • UC Davis project
    • Subcontracted to commercial firm
    • design is not robust
      • component variation
      • external noise on threshold
      • parasitic C on SIFT output
  • SVX 2 has problems in MCM package
what s changed
What’s Changed?
  • Biggest change is in FPGAs
    • Emulate SVX II for readout
    • Buffer 64 or 128 data points
    • Zero suppress the data on the fly.
  • Fast and inexpensive FLASH ADC converters
  • Existence of .25 micron designs at FNAL that can be dropped in to new chip designs
3 options
3 options
  • Direct SIFT replacement
  • SIFT replacement but include pipeline (18 channel)
  • Replace entire MCM without using the SVX II chip.
direct replace
Direct Replace
  • Requires replacement of SIFT in existing MCM’s
  • Potentially the lowest cost
    • may have yield problems
  • Keeps problems with SVX
    • Input is always open
    • differential non linearity
  • Requires a lot of FNAL manpower
  • New process that has a great deal of unknown risks
sift pipeline
SIFT+Pipeline
  • Only change is to add the pipeline delay to the SIFT
    • Allows the SVX to be cleared before charge transfer
    • Eliminates SVX pickup
new mcm
NEW MCM
  • Mux analog out to a flash ADC
    • 10 bit Flash ADC, 2 channels/chip
    • 3 micro s total conversion time
      • allows 94 ns/conversion
  • Chip control from an FPGA
  • Make daughter board same footprint as MCM
  • Power consumption appears similar to current MCM
  • Solves both CFT and preshower in one board
details
Details
  • Pipe line is in 0.25 micron.
    • convert preamp to 0.25
    • should part be made rad hard?
  • Use gate array to zero suppress and put data into SVX format
    • how to pack 10 bits into format.
  • Do we need 2 disc. levels?
    • If yes, how does it get to virtual SVX.
  • Do we implement digital controls?
    • how is down loading done?
  • How is power handled?
schedule and cost
schedule and cost
  • TSMC submission in November
    • $175K for 10 wafers (6 guaranteed)
    • Share submission with BTEV pixel
    • get enough chips for project (if OK)
      • ~1000 chips/wafer
    • Packaging cost is $5/chip $15K
    • chip testing done at FNAL ~$30K
  • dual 12 bit ADC and FPGA for $30
  • Daughter board+stuffing for $50.
    • pair of adapter boards cost $75.
  • Total for 2000 is $160K
    • Is 2000 enough?
  • Need 50% contingency at this stage
  • $307K total without TSMC cost
    • incremental cost over SIFT only is ~$200K assuming labor at FNAL is free.
  • Done 1 year after submission
    • need to cycle all AFE boards
which option
Which Option?
  • FADC gets rid of DNL and readout problems.
  • Also reduces risk for changing the SIFT parts on MCM’s
  • FADC gives clean solution to CFT and Preshower
  • But, it costs more money.
  • Both solutions probably take the same time
    • SIFT replacement is more of an unknown
    • Need to try SIFT repair on 50 parts ASAP.
  • Chip designer needs to know what to do by the end of May
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