Monolithic Pixel Sensor in SOI Technology - First Test Results

1. Monolithic Pixel Sensor in SOI Technology - First Test Results H. Niemiec, M. Koziel, T. Klatka, W. Kucewicz, S. Kuta, W. Machowski, M. Sapor University of Mining and Metallurgy, Krakow K. Domanski, P. Grabiec, M. Grodner, B. Jaroszewicz, A. Kociubinski, K. Kucharski, J. Marczewski, D. Tomaszewski Institute of Electron Technology, Warszawa M. Caccia University of Insubria, Como Presented by Halina Niemiec

2. At Prague • The concept of SOI active pixel sensor realized in wafer-bonded SOI substrate was presented • The technology development: technological challenges, test structures and experiments were described Detector handle wafer • High resistive • 300 m thick Electronics active layer • Low resistive • 1.5 m thick

3. Progress of the project • Fabrication of SOI test structure (TS - SOI) was completed • First run – only standard CMOS devices produced • Second run – cavities for pixel junction created • Prototype readout circuits in commercial technology were delivered • First measurements of TS-SOI and prototype chips performed

4. SOI Test Structures TS-SOI chip • General technological test structures for parameters extraction, investigation of device mismatches, process control, reliability test • Examples of analogue and digital circuits for comparison simulation and measurements results • Specific test structures for SOI detector applications First two runs were performed on low resistive SOI substrates and no pixel junctions were produced.

5. TS-SOI – Results • Reliability test structures • Chain of contact windows to the detectors • Metal1 serpentine over deep detector cavities The measurements indicated continuous electrical paths

6. TS-SOI – Results Examples of measured MOS characteristics PMOS W/L=20m/10m NMOS W/L=20m/10m

7. TS-SOI – Results Technological mismatch studies Measurements of test structure consisting of current mirrors with exactly the same dimensions – neighbouring and distant devices investigated Detailed measurements performed for left side of a wafer with 1.5 m thick active layer Left and right side of the wafer differs by implantation dose.

8. 50m/10 m TS-SOI – Results NMOS transistors W/L=50m/10 m 15m/3 m W/L=15m/3 m

9. TS-SOI – Results PMOS transistors 50m/10 m W/L=50m/10 m 15m/3 m W/L=15m/3 m

10. LEVEL=1 LEVEL=2 KP= 2.293E - 5 VTO= 0.991 VTO= 0.688 GAMMA= 0.868 GAMMA= 0.633 PHI= 1.241 PHI= 0.969 PB= 0.600 LAMBDA= 0.059 NFS= 1.000E+9 UO= 1.547E+3 UCRIT= 3.242E+4 UEXP= 0.447 LAMBDA= 0.041 VMAX= 1.000E+7 NEFF= 2.048 DELTA= 0.000 TS-SOI – Model extraction Extracted MOS models for first run of TS-SOI: level 1 and level 2. Extraction of level 3 model in progress. Characteristics simulated with level 2 model fit quite well measurements results

11. TS-SOI – Results • DC characteristics were measured for digital cells (inverter, double load inverter, double load buffer, NAND and NOR gate) and simple amplifying stages (OS and OS-OG) • Obtained characteristics will be used for device models validation

12. TS-SOI – Results Inverter: VT  2.5 V Max IVDD=160 A OS amplifier: Gain  -168 V/V @ 3 mA Gain  -102 V/V @ 11 mA

13. TS-SOI – Next steps • Further works on technological files extraction and device mismatches studies • Measurements of readout matrix (with input pads) in SOI technologies • Production of test structures on high resistive substrates (already in progress) and measurements of complete sensors

14. Prototype readout circuits First prototype of the readout circuit was designed and fabricated in 0.8 AMS technology • Architecture of a readout circuit isbeing tested before the technological works are finished • Technology properties and the readout circuit operation are investigated separately Compatibility was obtained by special design techniques: • Re-scaling transistor dimensions to obtain the same gate capacitances and width to length (W/L) ratios like in IET-SOI technology • Using most crucial IET-SOI design rules for the layout – the same drain diffusion areas, the same metal lines widths

15. Architecture of prototype chip The prototype readout circuit consists of 2 matrices with 256 (16x16) channels. Detecting diode is replaced by injection capacitance.

16. Prototype chip • Implemented readout technique combines rolling-shutter with CDS • Detector dead time is limitedto the reset time of integrating element • Integration time of every channel is adjustable and well defined

17. Prototype chip - Results Transfer characteristic Output range: 1.75 V Nonlinearity: 5%

18. Prototype chip – Next steps • Further validation of prototype readout circuits • Estimation of maximum readout speed • Investigation of possible parasitic effects, like cross-talk, gradient across the circuit, etc. • Basing on the results of prototype chips measurements the readout circuit in SOI technology will be designed