CP208 Digital Electronics Class Lecture 11 May 13, 2009. In This Class. We Will Discuss : Chapter 11: Memory and Advanced Digital Circuits. Memory and Advanced Digital Circuits. 3. Introduction.
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CP208Digital ElectronicsClass Lecture 11May 13, 2009
We Will Discuss:
Memory and Advanced Digital Circuits
Memory and Advanced
11.1.1 The Latch
Three Operating Points A, B, and C.
Two Stable Operating Points, A and C.
At C: vW = vZis High,
vX = vYis Low.
At A: Reverse is True.
Now, X and Z are Latch Out Puts.
In State A: vXis High (VOH) and vZis Low (VOL).
In State C: vXis Low (VOL) and vZis High (VOH).
Thus, Latch is Bistable Ckt having Two Complementary Outputs
Latch with a Triggering Mechanism/Circuitry forms a …
… Flip – Flop
Simplest Flip-Flop is Set/Reset (SR) Flip-Flop…
Second Input of each NOR
Gate Labeled as S and R
serve as Trigger
Set State (Storing 1): When
Reset State (Storing 0): Opposite of Set
Rest or Memory State (when we do not wish to change state of Flip-Flop) : Both S and R inputs Low
Consider the Case When Flip-Flop is Storing Logic 0
Since Q is low, Both inputs to G2 will be Low and its Output will therefore be High.
High Output of G2 is applied to Input of G1, causing its Output Q to be Low (since R is Low), satisfying the Original Assumption.
To SetFlip-Flop [To Store Logic 1]
Raise S to Logic-1 Level While Leave R at 0.
Output of G2 to 0 or Low.
Two Inputs of G1 will be 0 or Low, causing its Output Q to be 1 or High.
Now, if S returns to 0 Flip-Flop remains Set. Raising S to 1 again will make No Change.
To ResetFlip-Flop [To Store Logic 0]
Raise R to Logic-1 Level While Leave S at 0.
SHOW… The Flip-Flop will be Forced to Reset State and will remain in This State even after R returns to 0. Raising R to 1 again will make No Change.
Note that the Trigger Signal Merely Starts Regenerative Action of the Positive-Feedback Loop of the Latch
What Happens When S=R=1 ???
Both NOR Gates will cause to become 0 making Complementary labeling Incorrect.
However, if R and S return to Rest State (R=S=0) precisely at the same time, the state of Flip-Flop will be undefined. For this reason this input Combination is Not Allowed.
In Practice one of the R and S returns to 0 first, and the Final State is determined by the input that Remains High Longest.
Qn is Value of Q at Time tn just before application of R and S Signals.
Qn+1 is Value of Q at time tn+1 after application of input Signals.
SR Flip-Flop can also be implemented using two NAND gates. In this case Set Reset Functions are active when Low, therefore labeled as
Clocked version of SR Flip-Flop using CMOS.
Except Clock Inputs, It operates exactly same as the Logic Circuit scheme.
Clock inputs form AND Function with S and R, therefore, Flip-flop can only be Set and Resent when Clock is High.
To Set from Reset State: High (VDD) Signal on S while R is Held at Low (0V). Now, When Clock Goes High both Q5 and Q6 will conduct, Pulling Voltage at Down. When V goes below threshold of (Q3,Q4) Inverter, It will begin switching states and V at Q node will Rise. The Increase at Q is Fed Back to the Input of (Q1, Q2) Inverter, causing its Output at to go down further. The regeneration process is in progress.
Flip-Flop switching (for Set) is predicted on following two assumptions:
1. Q5 and Q6 supply sufficient current to pull node Q at least slightly below threshold of (Q3 and Q4) inverter. This is very important for the regenerative process to begin. Example 11.1 investigates minimum W/L ratios so that Q5 and Q6 must meet this requirement.
2. The Set signal remains high for an interval long enough to cause regeneration to take over the switching process. An estimate of minimum width required for the set pulse can be obtained as the Sum of Interval during which voltage at is reduced from VDD to VDD/2 and the interval for the voltage at Q to respond and rise to VDD/2
Finally, due to symmetry all remarks apply equally well to Reset process.
We Will Discuss:
RAM and ROM Memories