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CYPRESS SEMICONDUCTOR

CYPRESS SEMICONDUCTOR. QDR Class vs DDR III (DRAM) . 9. 9. 9. 9. 9. 9. 9. 9. 20 Address Bus (Broadside) . 14 Multiplexed Address Bus (Row & Col) . 3 Address Bus (Bank) . Common I/O . Data Out . Data In. QDR2+ SRAM. 8. DDR3 SDRAM. 8.

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CYPRESS SEMICONDUCTOR

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  1. CYPRESSSEMICONDUCTOR

  2. QDR Class vs DDR III (DRAM) 9 9 9 9 9 9 9 9 20 Address Bus (Broadside) 14 Multiplexed Address Bus (Row & Col) 3 Address Bus (Bank) Common I/O Data Out Data In QDR2+ SRAM 8 DDR3 SDRAM 8 QDR2 supports simultaneous Reads and Writes Both at Double Data Rate for 4.3GB/s/Port x 2 Ports = 9.6GB/s @533MHz DDR3 supports separate Read and Write at Double Data Rate for 2.13GB/s/Port x 1 Port = 2.13GB/s @533MHz Broadside addressing offers same access time from anywhere in the memory core Multiplexed addressing causes variable access times in the memory core

  3. Stratix IV FPGA Memory ComparisonQDR vs DDRIII DRAM • 2X Pin Bandwidth Improvement • 4X Data Rate Improvement Source Altera Stratix IV Data Sheet

  4. Stratix IV FPGA Memory ComparisonQDR vs DDRIII DRAM (cont) • (2) DDR3 x16 + (1) DDR3 x8) • DIMM Module Socket • (1) QDRII+ x36 Reduced Board Space • 4.4 x Latency Improvement

  5. Stratix IV FPGA Memory ComparisonQDR vs DDRIII DRAM (cont) • SRAM Access is Deterministic

  6. Additional Features to Compare “Cost of Ownership” • 1 Chip vs Multi Chip Module (Units, sockets) • Added cost for Module Printed Circuit Board • Cost of High Frequency Socket • Soldering vs Socket • Support for system level Error Correction (ECC) to improve reliability to field related failures • Soft error detection and correction • Self Healing for some Hard and Soft bit errors • 1 SRAM supports 36b • 3 DRAM required for 36b (16+16+4)

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