Switch-Level Modeling. How to describe a switch-level circuit ?. Verilog Switch Primitives. Modeling transistor networks at the switch-level more accurately represents their operation. Verilog provides unidirectional and bidirectional primitives that you can use to model the switch networks:
How to describe a switch-level circuit ?
Modeling transistor networks at the switch-level more accurately represents their operation.
Verilog provides unidirectional and bidirectional primitives that you can use to model the switch networks:
cmos nmos pmos pullup
rcmos rnmos rpmos pulldown
tran tranif0 tranif1
rtran rtranif0 rtranif1
cmos (drain, source, ngate, pgate)
tranif0 (data1, data2, control);
tranif1 (data1, data2, control);
You can assign delays to some switch types:
coms #(<delay>) (d, s, ng, pg);
nmos #(<rise_delay>,<fall_delay>) (d, s, g);
pmos #(<rise_delay>,<fall_delay>),<turnoff_delay>) (d, s, g);
delays,but no source-drain channel delays
tranif0 #(<delay>) (d, s, g);
tranif1 #(<turnon_delay>,<turnoff_delay>) (d, s, g);
Note: You can specify delays in min:typ:max format.
You can assign strengths to some primitive types:
the simulator ignores the unneeded strength specification
pullup (weak1, weak0) (net1);
You must specify both drive strengths,or none
nand (highz1, strong) (net1,net2,net3);
trireg (small) net1;
Level 7 6 5 4 3 2 1 0
Drive supply strong pull weak highz
Charge large medium small
The switches can reduce the strength of signals passing through them:
supply strength signal to a strong signal
signal strength according to the following table:
Input strength Reducel strengh
7 – supply 5 – pull
6 – strong 5 – pull
5 – pull 3 – weak
4 – large 2 – medium
3 – weak 2 – medium
2 – medium 1 – small
1 – small 1 – small
0 – highz 0 – highz
Switch networks may contain unidirectional and bidirectional switches.
Verilog-XL partitions switch-level networks into channel-connected regions.
Use the Switch-XL algorithm to:
--- The XL algorithm does not accelerate bidirectional switches
Use the +switchxl option to globally enable the Switch-XL algorithm.
verilog source.v +switchxl
Use the `switch compiler directive to selectively enable the Switch-XL algorithm.
// control networks here
// datapath networks here
Use the Switch-XL algorithm:
---For a significantly –sized network of bidirectional switches
---For a network of switches you cannot otherwise correctly functionally model with
only 2 switch drive strengths and 4 (including none)net charge strengths
Use the default algorithm:
---For a network of densely-packed significantly-sized regularly-structured
The drive strength expression must evaluate to a number from 1 to 250.
These statements declare tran switches and assign relative drive strengths.
Switch t1 has the largest conductance relative to t0 and rt.
tranif1 strength(3) t1 (s0,d0,g0);
tranif0 strength(2) t0 (s1,d1,g1);
rtran strength(1) rt (s2,d2);
The charge strength expression must evaluate to a number from 0 to 250.
These statements declare trireg nets and assign relative charge strengths.
Net a has the largest capacitance relative to b,c and d.
trireg strength(25) a;
trireg strength(10) b;
trireg strength(5) c;
trireg strength(1) d;
The Switch-XL and default algorithms reduce signal strength differently:
--- Reduces signal strength by 0,1,or 2 levels for each switch instance
--- An rtran reduces a weak drive to a medium charge
--- Treats all drive strengths as higher than charge strengths
--- Maps standard strengths into the range of network strengths
--- Reduces strength once (by the highest resistance) in the channel
The Switch-XL algorithm performs the following steps:
1. Detects channel-connected switch networks containing at least one
2. Converts the timing model of unidirectional switches in these networks from the
rise/fall/turn-off model to the turn-on/turn-off model of bidirectional switches
3. Optimizes these networks,including removing nets
4. Compiles these networks into accelerative expressions for the XL engine
Switch-XL can remove net n1
In channel-connected regions containing at least one bidirectional switch,
Switch-XL converts the unidirectional switch timing model to the bidirectional
switch timing model,so that it can accelerate the region:
--- The rise delay becomes the turn-on delays,fall becomes turn-off
--- The smaller of the rise and fall delays becomes the turn-on delay
timing model converted
In this section, you learned about:
1. Name the Verilog bidirectional primitives.
2. How do the delay models for the unidirectional and
bidirectional switches differ?
3. A Verilog-XL switch-level network contains which
types of switches?
4. What is the range of charge strengths you can assign
to a Switch-XL trireg net?
5. How does Switch-XL reduce signal strength in channel?