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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

CARLOS MANUEL ANDRIL NEIVA DANIEL JOAO MONIZ CORREIA. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; package modules_states is type MODULE_TYPE is (z0, z1, z2, z3);

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

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  1. CARLOS MANUEL ANDRIL NEIVA DANIEL JOAO MONIZ CORREIA library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; package modules_states is type MODULE_TYPE is (z0, z1, z2, z3); type STATE_TYPE is (a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10); type ARRAY_OF_LOGIC is array (natural range <>,natural range <>) of std_logic; type SA_OF_LOGIC is array (natural range <>) of std_logic; end modules_states; package body modules_states is end modules_states;

  2. ---------------------------------- for stack of modules begin type Mstack is array(0 to stack_size) of MODULE_TYPE; signal M_stack : Mstack; ---------------------------------- for stack of modules end signal NM_FS : STATE_TYPE; -- New Module First State signal LEFT : std_logic; ---------------------------------- for modules signal col : integer range 0 to width-1; signal min : integer range 0 to width; signal max : integer range 0 to width; signal mcol : integer range 0 to width-1; signal mlin : integer range 0 to width-1; signal num : integer range 0 to width; signal row : integer range 0 to width-1; signal maskct : SA_OF_LOGIC(0 to width-1); begin ---------------------------------- for stack begin process(clk,rst) begin if rst = '1' then elsif rising_edge(clk) then end if; end process; process(clk,rst) begin if rst = '1' then stack_counter <= 0; FSM_stack(stack_counter) <= a0; M_stack(stack_counter) <= z0; error <= '0'; elsif rising_edge(clk) then if inc = '1' then if stack_counter = stack_size then error <= '1'; else stack_counter <= stack_counter + 1; FSM_stack(stack_counter+1) <= a0; FSM_stack(stack_counter) <= NS; M_stack(stack_counter+1) <= NM; end if; elsif dec = '1' then stack_counter <= stack_counter - 1; else FSM_stack(stack_counter) <= NS; end if; end if; end process; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.modules_states.ALL; entity HFSM is generic ( width :integer := 10; stack_size : integer := 3); port ( clk : in std_logic; rst : in std_logic; error : buffer std_logic; Matrix : in ARRAY_OF_LOGIC(0 to width-1,0 to width-1); linha : out integer range 0 to width-1; coluna : out integer range 0 to width-1; maskc : out SA_OF_LOGIC(0 to width-1); maskl : out SA_OF_LOGIC(0 to width-1); masklt : out SA_OF_LOGIC(0 to width-1); numero : out integer range 0 to width; ready : out std_logic); end HFSM; architecture Behavioral of HFSM is -- modules begin --type MODULE_TYPE is (z0, z1); signal NM,CM: MODULE_TYPE; -- modules end -- FSM module begin --type STATE_TYPE is (a0, a1, a2, a3, a4, a5); signal NS,CS: STATE_TYPE; -- FSM module end ---------------------------------- for stack begin type stack is array(0 to stack_size) of STATE_TYPE; signal FSM_stack : stack; signal stack_counter, saved_stack_counter : integer range 0 to stack_size; signal inc : std_logic; signal dec : std_logic; signal unwinding : integer range 0 to stack_size; ---------------------------------- for stack end

  3. when z1 => case FSM_stack(stack_counter) is when a0 => ready <= '0'; inc <= '0'; dec <= '0'; col <= 0; min <= width; max <= 0; mcol <= 0; NS <= a1; when a1 => dec <= '0'; if maskct(col) = '1' then inc <= '0'; else inc <= '1'; end if; NS <= a2; NM <= z2; when a2 => dec <='0'; inc <='0'; if num < min then mcol <= col; min <= num; end if; if col = (width-1) then NS <= a3; else col <= col+1; NS <= a1; end if; when a3 => dec <='0'; inc <='0'; row <= 0; mlin <= 0; NS <= a4; when a4 => dec <='0'; if Matrix(row,mcol)='1' then NS <= a5; NM <= z3; inc <='1'; else inc <= '0'; NS <= a5; end if; when a5 => dec <='0'; inc <='0'; if num > max then mlin <= row; max <= num; end if; CM <= M_stack(stack_counter); CS <= FSM_stack(stack_counter); ---------------------------------- for stack end -- FSM module begin process (clk) --CM,CS,Matrix, stack_counter) skl begin if falling_edge(clk) then -- skl case M_stack(stack_counter) is when z0 => case FSM_stack(stack_counter) is when a0 => ready <= '0'; inc <= '0'; dec <= '0'; col <= 0; min <= width; max <= 0; mcol <= 0; NS <= a1; linha <= 0; coluna <= 0; numero <= 0; maskc <= ('0','0','0','0','0','0','0','0','0','0'); maskl <= ('0','0','0','0','0','0','0','0','0','0'); masklt <= ('0','0','0','0','0','0','0','0','0','0'); maskct <= ('0','0','0','0','0','0','0','0','0','0'); when a1 => inc <= '1'; dec <= '0'; NM <= z1; NS <= a2; when a2 => inc <='0'; dec <='0'; masklt(mlin) <= '1'; for i in 0 to width-1 loop if Matrix(mlin,i)='1' then maskct(i)<='1'; end if; end loop; if maskct = ('1','1','1','1','1','1','1','1','1','1') then NS <= a5; else NS <= a1; end if; when a5 => ready <= '1'; when others => null; end case;

  4. if row = (width-1) then NS <= a6; else row <= row+1; NS <= a4; end if; when a6 => dec <='0'; inc <='0'; maskc(mcol)<='1'; maskl(mlin)<='1'; NS <= a7; col <=0; when a7 => dec <='0'; inc <='0'; if Matrix(mlin,col)='1' then maskc(col)<='1'; end if; NS <= a8; when a8 => dec <='0'; inc <='0'; if col = (width-1) then NS <= a9; else col <= col+1; NS <= a7; end if; when a9 => dec <='1'; inc <='0'; linha <= mlin; coluna <= mcol; numero <= max; when others => null; end case; ------------------------------------------------------------------------------ when z2 => case FSM_stack(stack_counter) is when a0 => inc <= '0'; dec <= '0'; num <= 0; row <= 0; NS <= a1; when a1 => dec <= '0'; inc <= '0'; if Matrix(row,col)='1' then num <= num+1; end if; NS <= a2; when a2 => dec <= '0'; inc <= '0'; if row = width-1 then NS <= a3; else NS <= a1; row <= row+1; end if; when a3 => dec <= '1'; inc <= '0'; when others => null; end case; ------------------------------------------------------------------------------ when z3 => case FSM_stack(stack_counter) is when a0 => inc <= '0'; dec <= '0'; num <= 0; col <= 0; NS <= a1; when a1 => dec <= '0'; inc <= '0'; if Matrix(row,col)='1' then num <= num+1; end if; NS <= a2; when a2 => dec <= '0'; inc <= '0'; if col = width-1 then NS <= a3; else NS <= a1; col <= col+1; end if; when a3 => dec <= '1'; inc <= '0'; when others => null; end case; when others => null; end case; end if; -- skl end process; -- FSM module end end Behavioral;

  5. 0 0 0 0 0 0 0 0 1 (('1','0','1','0','0','0','0','0'), ('0','0','1','1','0','0','0','0'), ('0','0','0','0','0','0','1','0'), ('1','0','0','0','0','0','0','0'), ('0','0','0','0','1','1','0','0'), ('0','0','0','1','0','1','0','0'), ('0','0','0','0','0','0','0','1'), ('1','0','1','0','0','0','0','0'), ('0','1','1','0','0','0','0','0') ) 0 0 0 0 1 0 0 0 1 (('1','0','1','0','0','0','0','0'), ('0','0','1','1','0','0','0','0'), ('0','0','0','0','0','0','1','0'), ('1','0','0','0','0','0','0','0'), ('0','0','0','0','1','1','0','0'), ('0','0','0','1','0','1','0','0'), ('0','0','0','0','0','0','0','1'), ('1','0','1','0','0','0','0','0'), ('0','1','1','0','0','0','0','0') ) (('1','0','1','0','0','0','0','0'), ('0','0','1','1','0','0','0','0'), ('0','0','0','0','0','0','1','0'), ('1','0','0','0','0','0','0','0'), ('0','0','0','0','1','1','0','0'), ('0','0','0','1','0','1','0','0'), ('0','0','0','0','0','0','0','1'), ('1','0','1','0','0','0','0','0'), ('0','1','1','0','0','0','0','0') ) (('1','0','1','0','0','0','0','0'), ('0','0','1','1','0','0','0','0'), ('0','0','0','0','0','0','1','0'), ('1','0','0','0','0','0','0','0'), ('0','0','0','0','1','1','0','0'), ('0','0','0','1','0','1','0','0'), ('0','0','0','0','0','0','0','1'), ('1','0','1','0','0','0','0','0'), ('0','1','1','0','0','0','0','0') ) 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1

  6. 0 1 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 1 (('1','0','1','0','0','0','0','0'), ('0','0','1','1','0','0','0','0'), ('0','0','0','0','0','0','1','0'), ('1','0','0','0','0','0','0','0'), ('0','0','0','0','1','1','0','0'), ('0','0','0','1','0','1','0','0'), ('0','0','0','0','0','0','0','1'), ('1','0','1','0','0','0','0','0'), ('0','1','1','0','0','0','0','0') ) (('1','0','1','0','0','0','0','0'), ('0','0','1','1','0','0','0','0'), ('0','0','0','0','0','0','1','0'), ('1','0','0','0','0','0','0','0'), ('0','0','0','0','1','1','0','0'), ('0','0','0','1','0','1','0','0'), ('0','0','0','0','0','0','0','1'), ('1','0','1','0','0','0','0','0'), ('0','1','1','0','0','0','0','0') )

  7. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; package empty is type matrix_type is array (integer range 1 to 9,1 to 8) of std_logic; end empty; package body empty is --begin end empty; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; use work.empty.all;

  8. entity Test_matrixIO is generic (stack_size : integer := 1; numberOFlines : integer := 9; -- number of matrix lines numberOFcolumns : integer := 8 ) ; -- number of matrix columns Port( rst : in std_logic; clk : in std_logic; error : out std_logic; test_matrix : out matrix_type; covering : out std_logic_vector(1 to numberOFlines); result : out natural range 0 to 64; MinCol : out natural range 0 to numberOFlines; MinColInd : out natural range 0 to numberOFcolumns; MaxOnesIndex: out natural range 0 to numberOFlines; MaxOnes : out natural range 0 to numberOFcolumns ); end Test_matrixIO; Architecture Beh of Test_matrixIO is -- these arrays help to count the number of ones in lines/columns type array_of_int_lines is array (integer range 1 to numberOFlines) of natural range 0 to numberOFcolumns; type array_of_int_columns is array (integer range 1 to numberOFcolumns) of natural range 0 to numberOFlines; -- these signals keep particular values signal number_of_ones_in_lines : array_of_int_lines; signal number_of_ones_in_selected_lines : array_of_int_lines; signal number_of_zeros_in_columns : array_of_int_columns;

  9. signal internal_covering : std_logic_vector(1 to numberOFlines) := "000000000"; -- matrix has to be declared here (the size 9 lines and 8 columns) signal define_matrix : work.empty.matrix_type := (('1','0','1','0','0','0','0','0'), ('0','0','1','1','0','0','0','0'), ('0','0','0','0','0','0','1','0'), ('1','0','0','0','0','0','0','0'), ('0','0','0','0','1','1','0','0'), ('0','0','0','1','0','1','0','0'), ('0','0','0','0','0','0','0','1'), ('1','0','1','0','0','0','0','0'), ('0','1','1','0','0','0','0','0') ); -- counts the number of ones in lines procedure NumberOfOnesInLines (input : work.empty.matrix_type; signal result : out array_of_int_lines) is variable tempInt : array_of_int_lines := (0,0,0,0,0,0,0,0,0); begin for i in 1 to numberOFlines loop --lines for j in 1 to numberOFcolumns loop --columns if input(i,j) = '1' then tempInt(i) := tempInt(i)+1; end if; end loop; end loop; result <= tempInt; end NumberOfOnesInLines;

  10. -- modules begin -- modules for HFSM type MODULE_TYPE is (z0, z1, z2, z3, z4, z5); signal NM: MODULE_TYPE; -- modules end -- FSM module begin -- states for HFSM type STATE_TYPE is (a0, a1, a2, a3, a4, a5, a6, a7); signal NS: STATE_TYPE; -- FSM module end ---------------------------------- for stack begin type stack is array(0 to stack_size) of STATE_TYPE; signal FSM_stack : stack; signal stack_counter : integer range 0 to stack_size; signal inc : std_logic; signal dec : std_logic; ---------------------------------- for stack end

  11. ---------------------------------- for stack of modules begin type Mstack is array(0 to stack_size) of MODULE_TYPE; signal M_stack : Mstack; ---------------------------------- for stack of modules end signal NM_FS : STATE_TYPE; -- New Module First State -- the index and the value of maximum number of ones signal MaxElement, MaxElementIndex : natural range 0 to numberOFlines := 0; -- the index and the value of maximum number of zeros signal MaxElement0, MaxElementIndex0 : natural range 0 to numberOFcolumns := 0; -- masks for lines and columns (for simplicity MaskLines were not used in this project) signal MaskLines : std_logic_vector(1 to numberOFlines) := "000000000"; signal MaskColumns : std_logic_vector(1 to numberOFcolumns) := "00000000"; -- number of ones in lines with selected columns

  12. procedure NumberOfOnesInLinesMinColumn (input : work.empty.matrix_type; signal result : out array_of_int_lines) is variable tempInt : array_of_int_lines := (0,0,0,0,0,0,0,0,0); begin for i in 1 to numberOFlines loop -- lines if (define_matrix(i,MaxElementIndex0) = '1') then for j in 1 to numberOFcolumns loop if (MaskColumns(j) = '0') then if input(i,j) = '1' then tempInt(i) := tempInt(i)+1; end if; end if; end loop; end if; end loop; result <= tempInt; end NumberOfOnesInLinesMinColumn; -- number of zeros in columns procedure NumberOfZerosInColumns (input : work.empty.matrix_type; signal result : out array_of_int_columns) is variable tempInt : array_of_int_columns := (0,0,0,0,0,0,0,0);

  13. begin for i in 1 to numberOFlines loop --lines for j in 1 to numberOFcolumns loop --columns if MaskColumns(j) = '0' then if input(i,j) = '0' then tempInt(j) := tempInt(j)+1; end if; else null; end if; end loop; end loop; result <= tempInt; end NumberOfZerosInColumns; begin NumberOfOnesInLines(define_matrix, number_of_ones_in_lines); --NumberOfZerosInColumns(define_matrix, number_of_zeros_in_columns); test_matrix <= define_matrix; ---------------------------------- for stack begin -- HFSM stack memory process(clk,rst) begin if rst = '1' then stack_counter <= 0; FSM_stack(0) <= a0; M_stack(0) <= z0; error <= '0';

  14. elsif rising_edge(clk) then if inc = '1' then if stack_counter = stack_size then error <= '1'; else stack_counter <= stack_counter + 1; FSM_stack(stack_counter+1) <= NM_FS; FSM_stack(stack_counter) <= NS; M_stack(stack_counter+1) <= NM; end if; elsif dec = '1' then stack_counter <= stack_counter - 1; else FSM_stack(stack_counter) <= NS; end if; end if; end process; ---------------------------------- for stack end -- FSM module begin -- HFSM combinational circuit and generating outputs process (clk) variable index : natural range 0 to numberOFlines; begin if falling_edge(clk) then

  15. case M_stack(stack_counter) is -- main module when z0 => case FSM_stack(stack_counter) is when a0 => inc <= '0'; dec <= '0'; NS <= a1; internal_covering <= (others => '0'); when a1 => inc <= '0'; dec <= '0'; NS <= a2; inc <= '1'; NM<=z1; NM_FS <= a0; NumberOfZerosInColumns(define_matrix, number_of_zeros_in_columns); when a2 => inc <= '0'; dec <= '0'; NS <= a3; NumberOfOnesInLinesMinColumn(define_matrix, number_of_ones_in_selected_lines); when a3 => inc <= '0'; dec <= '0'; NS <= a4; inc <= '1'; NM<=z2; NM_FS <= a0; when a4 => inc <= '0'; dec <= '0'; NS <= a5; for j in 1 to numberOFcolumns loop --columns MaskColumns(j) <= MaskColumns(j) or define_matrix(MaxElementIndex,j); end loop; internal_covering(MaxElementIndex) <= '1'; when a5 => inc <= '0'; dec <= '0'; if MaskColumns = "11111111" then NS <= a6; else NS <= a1; end if; when a6 => inc <= '0'; dec <= '0'; NS <= a6; when others => null; end case;

  16. -- finds a column with minimal number of ones when z1 => case FSM_stack(stack_counter) is when a0 => inc <= '0'; dec <= '0'; index := 1; MaxElement0 <= 0; if (number_of_zeros_in_columns(index) > MaxElement0) then NS <= a1; else NS <= a2; end if; when a1 => inc <= '0'; dec <= '0'; MaxElement0 <= number_of_zeros_in_columns(index); MaxElementIndex0 <= index; NS <= a3; when a2 => inc <= '0'; dec <= '0'; NS <= a3; when a3 => inc <= '0'; dec <= '0'; if index = numberOFcolumns then NS <= a4; else index := index+1; if number_of_zeros_in_columns(index) > MaxElement0 then NS <= a1; else NS <= a2; end if; end if; when a4 => inc <= '0'; dec <= '0'; NS <= a4; if stack_counter > 0 then dec <= '1'; else dec <= '0'; end if; when others => null; end case;

  17. -- finds a line with maximal number of ones and with ones in the selected in z1 column when z2 => -- finds for minimal column an element with maximum number of ones/zeros case FSM_stack(stack_counter) is when a0 => inc <= '0'; dec <= '0'; index := 1; MaxElement <= 0; NS <= a5; when a5 => inc <= '0'; dec <= '0'; if (number_of_ones_in_selected_lines(index) > MaxElement) then NS <= a1; else NS <= a2; end if; when a1 => inc <= '0'; dec <= '0'; MaxElement <= number_of_ones_in_selected_lines(index); MaxElementIndex <= index; NS <= a3; when a2 => inc <= '0'; dec <= '0'; NS <= a3; when a3 => inc <= '0'; dec <= '0'; if index = numberOFlines then NS <= a4; else index := index+1; if number_of_ones_in_selected_lines(index) > MaxElement then NS <= a1; else NS <= a2; end if; end if; when a4 => inc <= '0'; dec <= '0'; NS <= a4; if stack_counter > 0 then dec <= '1'; else dec <= '0'; end if; when others => null;

  18. end case; when others => null; end case; end if; end process; -- FSM module end -- assigning output signals MaxOnesIndex <= MaxElementIndex; MaxOnes <= MaxElement; MinColInd <= MaxElementIndex0; MinCol <= numberOFlines-MaxElement0; covering <= internal_covering; end Beh;

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