Bruce Mayer, PE Registered Electrical &amp; Mechanical Engineer [email protected]

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Engineering 43. Chp 6.4 RC OpAmps Ckts. Bruce Mayer, PE Registered Electrical &amp; Mechanical Engineer [email protected] RC OpAmp Circuits. Introduce Two Very Important Practical Circuits Based On Operational Amplifiers Recall the OpAmp. The “Ideal” Model That we Use R O = 0

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Engineering 43

Chp 6.4RC OpAmps Ckts

Bruce Mayer, PE

Registered Electrical & Mechanical [email protected]

RC OpAmp Circuits
• Introduce Two Very Important Practical Circuits Based On Operational Amplifiers
• Recall the OpAmp
• The “Ideal” Model That we Use
• RO = 0
• Ri = ∞
• Av = ∞
• Consequences of Ideality
• RO = 0  vO = Av(v+−v−)
• Ri = ∞  i+ = i− = 0
• Av = ∞  v+ = v−

=

v

0

+

RC OpAmp Ckt  Integrator
• KCL At v- node
• By Ideal OpAmp
• Ri = ∞  i+ = i- = 0
• Av = ∞  v+ = v- = 0
RC OpAmp Integrator cont
• Separating the Variables and Integrating Yields the Solution for vo(t)
• By the Ideal OpAmp Assumptions
• Thus the Output is a (negative) SCALED TIME INTEGRAL of the input Signal
• A simple Differential Eqn

KVL

=

v

0

+

RC OpAmp Ckt  Differentiator
• By Ideal OpAmp
• v- = GND = 0V
• i- = 0
• KCL at v-
• Now the KVL
RC OpAmp Differentiator cont.
• Recall the Capacitor Integral Law
• Recall Ideal OpAmp Assumptions
• Ri = ∞  i+ = i- = 0
• Av = ∞  v+ = v- = 0
• Then the KCL
• Thus the KVL
• Taking the Time Derivative of the above
RC OpAmp Differentiator cont
• Examination of this Eqn Reveals That if R1 were ZERO, Then vO would be Proportional to the TIME DERIVATIVE of the input Signal
• in Practice An Ideal Differentiator Amplifies Electrical Noise And Does Not Operate
• The Resistor R1 Introduces A Filtering Action.
• Its Value Is Kept As Small As Possible To Approximate A Differentiator
• In the Previous Differential Eqn use KCL to sub vO for i1
• Using
ALL electrical signals are corrupted by external, uncontrollable and often unmeasurable, signals. These undesired signals are referred to as NOISE

Signal

Signal

Noise

Noise

Aside → Electrical Noise
• The Signal-To-Noise Ratio
• Use an Ideal Differentiator
• Simple Model For A Noisy 1V, 60Hz Sinusoid Corrupted With One MicroVolt of 1GHz Interference
• The SN is Degraded Due to Hi-Frequency Noise
Class Exercise  Ideal Differen.
• Let’s Turn on the Lites for 10 minutes for YOU to Differentiate
• Given the IDEAL Differentiator Ckt and INPUT Signal
• Find vo(t) over 0-10 ms
• Given Input v1(t)
• SAWTOOTH Wave
• Recall the Differentiator Eqn

R1 = 0; Ideal ckt

RC OpAmp Differentiator Ex.
• The Slope from 0-5 mS
• Given Input v1(t)
• For the Ideal Differentiator
• Units Analysis
RC OpAmp Differentiator cont.
• Derivative Scalar PreFactor
• A Similar Analysis for 5-10 mS yields the Complete vO

OutPut

InPut

• Apply the Prefactor Against the INput Signal Time-Derivative (slope)
RC OpAmp Integrator Example
• For the Ideal Integrator
• Given Input v1(t)
• SQUARE Wave
• Units Analysis Again
RC OpAmp Integrator Ex. cont.
• 0<t<0.1 S
• v1(t) = 20 mV (Const)
• The Integration PreFactor
• 0.1t<0.2 S
• v1(t) = –20 mV (Const)
• Next Calculate the Area Under the Curve to Determine the Voltage Level At the Break Points
• Integrate In Similar Fashion over
• 0.2t<0.3 S
• 0.3t<0.4 S
RC OpAmp Integrator Ex. cont.1
• Apply the 1000/S PreFactor and Plot Piece-Wise
Practical Example
• Simple Circuit Model For a Dynamic Random Access Memory Cell (DRAM)
• Note How Undesired Current Leakage is Modeled as an I-Src
• Also Note the TINY Value of the Cell-State Capacitance (50x10-15 F)
Practical Example cont
• During a WRITE Cycle the Cell Cap is Charged to 3V for a Logic-1
• Thus The TIME PERIOD that the cell can HOLD the Logic-1 value
• The Criteria for a Logic “1”
• Vcell >1.5 V
• Now Recall that V = Q/C
• Or in terms of Current
• Now Can Calculate the DRAM “Refresh Rate”
Practical Example cont.2
• Consider the Cell at the Beginning of a READ Operation
• When the Switch is Connected Have Caps in Parallel
• Then The Output
• Calc the Change in VI/O at the READ
Design Example
• Examine the Reln to find an

Integrator

The Proposed SolutionDesign Example
• The by Ideal OpAmps & KCL & KVL &Superposition
Design Example
• The Ckt Eqn
• Then the Design Eqns
• This means that we, as ckt designers, get to PICK 3 values
• For 1st Cut Choose
• C = 20 μF
• R1 = 100 kΩ
• R4 = 20 kΩ
• TWO Eqns in FIVE unknowns
In the Design EqnsDesign Example

20μ

20k

20k

100k

10k

• If the voltages are <10V, then all currents should be the in mA range, which should prevent over-heating
• Then the DESIGN
WhiteBoard Work
• Let’s Work These Probs

80k

choose C such that

Find Energy Stored on Cx

### APPENDIX

IC GROUND BOUNCE

LEARNING EXAMPLE

FLIP CHIP MOUNTING

IC WITH WIREBONDS TO THE OUTSIDE

GOAL: REDUCE INDUCTANCE IN

THE WIRING AND REDUCE THE

“GROUND BOUNCE” EFFECT

A SIMPLE MODEL CAN BE USED TO

DESCRIBE GROUND BOUNCE

MODELING THE GROUND BOUNCE EFFECT

IF ALL GATES IN A CHIP ARE CONNECTED TO A SINGLE GROUND THE CURRENT

CAN BE QUITE HIGH AND THE BOUNCE MAY BECOME UNACCEPTABLE

USE SEVERAL GROUND CONNECTIONS (BALLS) AND ALLOCATE A FRACTION OF

THE GATES TO EACH BALL