Electrical Design C. Paul Earle May 8, 2009

1. Critical Angle Transmission (CAT) X-Ray Grating Spectrometer (XGS) for the International X-Ray Observatory (IXO) ~ Concept Presentation ~ Electrical Design C. Paul Earle May 8, 2009

2. Functional Block Diagram RIU Instrument Main Electronics (~ 25deg.C) Readout Electronics +28V Supply Focal Plane Digitizers (16) RS422 32(1Kx1K)pix CCD Arrays + driver FETs LVDS H/K & Thermal Timing (1pps) +28V Time Stamp & packetization (DEA) Spacecube Processor & Memory C&DH + Science Data PID Thermal Control Spacewire DC/DC Converter (DPA) +28V Survival Power Figure 1.

3. Detector Assumptions & Data Rate Readout Data Rate: Assume 14.7Hz frame rate @ 12bits/pix + 4bits/pix PCode and 8:1 row summation for each detector • Readout Rate ~ (1024x1026)pix/frame x (16bits/pix) x (14.7frames/sec)/8 ~ 30.8Mbps + each detector • 32x30.8Mbps ~ 988.4Mbpstotal to the DPA(ie. Main Electronics Box) ie. • ~ 61.8Mbpseach of 16 LVDS channels to the SpaceCube processor in the DPA(ie. Main Electronics Box) Given: DPA Output Data Rate ~ 128Kbps average to SSR, and 1.28Mbps for 6 hours per month. Data Storage: ~ 128Kbps x (24hours x 60min/hour x 60sec/min) ~ 11Gbits SSR for 24 hour storage Reverse Engineering: 128Kbps/32 arrays ~ 4Kbps per array @ 16bits/pix • 4Kbps/(16bits/pix) ~ 250pix/sec @ (5x5)pix/event • 250pix/sec/(25pix/event) ~ 10 events/sec per array, and 100 events/sec per array for 6 hours each month. • 10 events/sec/(14.7Hz/frame) ~ 0.7 events/frame Focal Plane Definition

4. SpaceCube 1.0 Processor

5. SpaceCube 2.0 Processor Interfaces SpaceCube 2.0 Processor cPCI LEON 3FT LVDS/SpaceWire 2.5 Gbyte FLASH SATA Ethernet SIRF Virtex 5 FX130T Multi-Gbps Transceivers 1.0 Gbyte RAM Multi-Gbps Transceivers PCIe/x8 SIRF Virtex 5 FX130T I2C/CAN/GPIO JTAG/Serial Debug

6. Flight Processor Comparison Notes: 1 – typical, 35 MIPS at 15 watts 2 – typical, 450 MIPS at 15 watts 3 – processor device only ... total board power TBD 4 – 3000 MIPS at 7.5 watts (measured) 5 – 5000 MIPS at 10 watts (calculated)

7. SpaceCube Size / Weight / Power

8. Customer Instrument Architecture Figure 2.

9. Revised Instrument Architecture Side A/Side B Redundancy H/K Data Heaters DPA Electronics Box 1 SpaceCube Card 1 Heater Control & H/K Card 1 LVPC Card (Side A) 1 SpaceCube Card 1 Heater Control & H/K Card 1 LVPC Card (Side B) (6 Cards Total) RIU DEA Box Readout & Digitizer Cards (16) Cameralink, Spacewire, LVDS (1pps) 16 channels 128 32 (1Kx1K) CCD Detector Arrays + driver FETS Spacewire 16 RS422 +28V(A) (power A) 4 outputs each CCD 2 CCDs each Card – 8 circuits Figure 3.

10. Detector Readout/Digitizer Electronics (8 circuits each board) Detector Readout Scheme (baseline) 5V 5V Rf (buffer) (12bits +4) Array (1 of 32) R1 4 (30.8Mbps) ADC (1Kx1K) pix (1 of 4 circuits) 500KHz Readout / Control FPGA 61.6Mbps avg. FIFO Rf (buffer) (12bits +4) (LVDS) Array (1 of 32) R1 4 (30.8Mbps) ADC (1Kx1K) pix control I/F (1 of 4 circuits) Master Clock 500KHz (1 of 16 Readout/Digitizer Boards, 8”x6”, 0.5Kg, 4W) – 8 circuits per board Note: Design Assumes Correlated Double Sampling (CDS) readout Figure 4a.

11. Alternative Detector Readout Scheme 5V Rf (buffer) (12bits +4) Array (1 of 32) R1 1 (30.8Mbps) ADC (1Kx1K) pix (1 of 8 channels) (0,1) 4Kbps avg each array. 500KHz Readout / Control FPGA (pixel processing) FIFO (LVDS) Vth (comparator) 8-12 bits DAC control I/F Master Clock Figure 4b. • Notes: • 1. FPGA identifies and stores the active pixels and 3x3 or 5x5 nearest neigbborhood. May require up to 5 consecutive rows of temporary storage. • 2. This Approach will not require high speed interfaces such as Camera link, or spacewire. RS422 will suffice. • 3. This approach will not require high throughput processors like Spacecube. A Coldfire processor will suffice. • 4. Vth can be adjusted in realtime on a per-pixel basis to correct for individual pixel biases.

12. in in cm cm in in Kg in in in cm cm cm m2 mm Kg/m3 Detector Electronics Assembly Box Sizing Box Mass & Size Spreadsheet

13. Detector Electronics Assembly Box Power Box Power Spreadsheet Note: The DEA box contains 2 power supply boards – 1A/1B (ie. 1 Prime / 1 Redundant)

14. Detector Electronics Assembly Box Summary Box Size: 23x18x48 cm3 (9” X 7” x 19”), 13.8Kg (ie. 10.6Kg board total + 3.2 Kg Housing)

15. in in cm cm in in Kg in in in cm cm cm m2 mm Kg/m3 Digital Processing Assembly (DPA) Box Sizing Box Mass & Size Spreadsheet

16. Digital Processing Assembly (DPA) Box Power Box Power Spreadsheet

17. DPA Electronics Box Summary Box Size: 23x18x18 cm3 (9” X 7” x 7”), 5.1Kg (ie. 3.6Kg board total + 1.5 Kg Housing)

18. Instrument Power Summary Spacecraft Power Bus Requirement

19. Harness Mass Estimates Harness Mass total ~ 8.5Kg

20. FPGA Costing Predefined Schema for Costing New FPGA Developments

21. FPGA Development Cost Information Predefined schema for costing new FPGA development Based on 11/26/07 email from Bill Lawson that summarizes in-house development estimates for custom FPGA algorithms following a discussing with Rick Schnurr and Terry Smith Parametric cost estimate includes the procurement costs for flight selected FPGAs from the manufacturer; NRE cost estimate includes the engineering labor to generate the algorithms $400K Minimum for FPGA Development 1.50 FTEs of New Code Design (VHDL coding and Simulation) 0.50 FTEs of New Code Verification (by Analysis) 0.25 FTEs of Signal Integrity Analysis (of all I/O lines) 0.25 FTEs of Lab Code Test $200K per Algorithm 1.00 FTEs of New Algorithm 0.25 FTEs of New Algorithm lab Test/Verification The most used FPGA on future missions is the Actel AX-2000 Many functions/algorithm that have been previously designed and coded, and are available as intellectual Property (IP) in VHDL Format. Implementing VHDL IP into an FPGA requires very little FTEs. IP developed by NASA is available for free IP from industry requires a license for its usage Examples of VHDL IP that are available Spacewire Data Network Protocol/interface PCI Data Bus Interface for both Bus Controller and Terminals Mil-STD-1553 Data Bus Controller and Remote Terminals Short Reed-Solomon Encoder/Decoder for Error Detection & Correction (EDAC) of Data in SEU vulnerable memory Rice Data Compression Algorithm (~2:1 Lossless) Pixel-Processor (for science data reduction) Downlink Formatting & Encoding CCSDS VCDU protocol Formatting Long Reed-Solomon Encoding for EDAC across downlink channels Convolution Encoding Randomization

22. FPGA Costs • As the customer team requested that the motors be costed separately from the instrument itself, this total was separated as it was included in the parametric cost presentation

23. Issues/Conclusion • Design assumes electrical redundancy for 5-10 year mission. • All motors/actuators have redundant means of activation. • Detectors and readout circuits are not redundant, but the design is fault tolerant due to the • flexibility of selecting either 2 or 4 readout channels for each of the 32 detectors. • There are redundant Power Supplies for the readout boards. • High Readout Data Rates (~1Gbps) requires high bandwidth interfaces such as LVDS, • Cameralink, or Spacewire. Signal integrity in the harnessing could be an issue, but solveable. • High Readout Data Rates requires high throughput processor(s) such as Spacecube. • It might be possible to do realtime filtering of the readout data in hardware (FPGA) to • reduce interface bandwidth and processor demands (see Figure 4b). • The Spacecube Processor will perform CCSDS packetization and milli-second granularity • time-stamping of the science data. The Processor will also perform close-loop PID heater • control. • A readout ASIC could be developed to reduce DEA Mass and Power, but will be more costly.

24. Post-Study Wrap-up Activity The CCD driver requirements from the Detectors Presentation suggests that the Electrical Presentation may not have sufficiently accounted for the power for the CCD digital clock drivers for the chosen detectors. The Detector discipline estimated that we would need 4 additional boards in the DEA to account for the digital clock drivers. Each of these boards would clock out 8 CCD arrays and require ~ 8W (ie. ~ 32Watts total for the 4 boards).

25. Backup Slides (Electrical Design Estimates)

26. Processor Board Startup ROM Spacecube Processor RAM EEPROM Memory (Data Processing) Time Stamp Function (2Khz counter) S/C 1pps RS422 I/F LVDS Drivers Spacewire I/F RIU Ethernet I/F S/W Development & Test Figure 5.

27. - - + + + + - - - - + + From Processor I+ I+ Heater Control circuit DAC From Processor V+ Heater Tsensor HK Mux Heater Current Heater Voltage + To Central HK - Tsensor Voltage Tsensor Current VRef ISource (1 of n circuits shown) Figure 6.

28. Housekeeping Board 1 1 1 1 1 1 1 14 Analog MUX Voltage sense Amplifier ADC (12-bits) FIFO Analog MUX 14 Analog MUX 8Kbps Amplifier Current sense 50spz 500Hhz 1 Amplifier To Coldfire Processor Housekeeping FPGA Analog MUX 1 mA source Temperature Sensors Analog De-MUX (1 of n sensors) Figure 7.

29. Power Converter & One-time Actuators (Power Supply Board, 8”x6”, 0.5Kg) Voltage Sense + - Current Sense + - I+ DC/DC Converter (~ 75% eff) +5v +12v +3.3v +28v FET Switch (or relay) One-time Actuators (n) FET Switch (or relay) Figure 8.