1 / 15

Extension of Asynchronous Design Automation Tools

Extension of Asynchronous Design Automation Tools. Michael Boyer Advisor: Cherrice Traver Steinmetz Symposium 2005. Introduction. Synchronous (clocked) Clock skew Asynchronous (self-timed). Advantages of Asynchronous. No clock skew problem Increased power efficiency

gaia
Download Presentation

Extension of Asynchronous Design Automation Tools

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Extension of Asynchronous Design Automation Tools Michael Boyer Advisor: Cherrice Traver Steinmetz Symposium 2005

  2. Introduction • Synchronous (clocked) • Clock skew • Asynchronous (self-timed)

  3. Advantages of Asynchronous • No clock skew problem • Increased power efficiency • Increased performance • Greater tolerance of variation in operating conditions • Greater frequency distribution of electromagnetic noise • Component modularity

  4. Real-World Examples • Amulet 1, 2e, 3, 3i • Oticon DigiFocus hearing aid • Philips 80C51 microcontroller • Intel RAPPID Project

  5. E E O E O O Phased Logic (PL) • Automated translation • Two phase LEDR signaling E

  6. Liveness and Safety • PL synthesis algorithm • Guarantees liveness and safety • Token abstraction

  7. Coarse-Grained PL • Wrap logic blocks with PL circuitry • Logic blocks: • Barrier blocks • Through blocks • Speed-up techniques: • Time borrowing • Early evaluation

  8. Wrapper Circuit

  9. VHDL Modeling • New models: • Wrapper models • Environment models • Assumptions • Testing

  10. ATACS • Automatic Timed Asynchronous Circuit Synthesis (ATACS) • Automated verification: • Hazard checking

  11. 100-200 ps Verification Example

  12. Results Wrapper for Through Blocks with Time Borrowing: min(D1, D2, D3, D4) + min(D5) ≥ max(C1) + max(xorG) + max(D-latch) – min(C2) – min(xorC) – min(DFF) min(D1, D2, D3, D4) + min(D5) ≥ max(compute) + max(D-latch) – min(C2) – min(xorC) – min(DFF) Wrapper for Through Blocks without Time Borrowing: min(D1, D2, D3, D4) ≥ max(compute) + max(D-latch) – min(nC2) – min(DFF) – min(nC1) Wrapper for Barrier Blocks without Early Evaluation: min(D1, D2, D3, D4) ≥ max(compute) + max(Data DFF setup time) – min(nC)

  13. Future Work • Include results in mapping tool • Use mapping tool to compare PL to synchronous • Implement PL in hardware

  14. Acknowledgements • Cherrice Traver, Union College • Chris Myers, University of Utah • Bob Reese, Mississippi State University • IBM/SRC

  15. Questions?

More Related