Novel Architectures

1. Novel Architectures Nigel Topham ICSA School of Informatics

2. Overview • Background • My research interests • ICSA research profile Team Talent Review - Nigel Topham

3. Brief bio • 85-89: Lecturer in Computer Science, Edinburgh • 90-91: Lead architect, ACRI, France • Multiprocessor GaAs supercomputer (Decoupled Access/Execute) • Compiler research followed • 92-99: Back at Edinburgh • Scalable VLIW architectures for embedded and DSP apps • Novel compiler + micro-architecture techniques • Founding director of ICSA • Left to form a startup • 99-03: Siroyan Ltd, co-founder and chief architect • Developed scalable VLIW DSP (OneDSP) • Delivered on-time, as synthesised Verilog IP • Highly-optimised compiler technology was key • Right-first-time 10million-gate silicon in 0.15um (and also 0.18um) • Proven in TSMC and UMC foundries • BlueLogic program • VC problems in 2002 curtailed development, IP sold to Altera • 03-03: ARC International, chief architect (ARC 600) Team Talent Review - Nigel Topham

4. OneDSP overview SR-8C • Scalable DSP + RISC • Configurable core: 2 to 16 MACS/~ • Clustered VLIW architecture • Partitioned register files • Register rotation (for s/w pipelining) • Predicated execution ( “ ) • Extensive SIMD capabilities • Low power synthesisable core • 0.1 mW / MHz / MAC @ 0.13um • 250 MHz worst-case • Sophisticated compiler technology • Combined software pipelining and register allocation • Peak performance achievable through compiled DSP code • Announced at MPF’01, product released on schedule SR-4C SR-2C 200mW, 2GIPS @ 250 MHz SR-1C 50mW, 500 MIPS @ 250 MHz Team Talent Review - Nigel Topham

5. 8 KB data cache 4-way associative 8 KB Instruction Cache 4-way associative IF DE RF EX WB A2 A1 + + sat sat sel sel 3:2 csa 3:2 csa tsu fetch align dec branch tsu read RF byp ALU merge wr cc miss Data 1 Data 2 tsu D-tag hit tsu D-data ext wr tsu RAM DSP 1 DSP 2 DSP 3 XY AGU XY mem opd sel 16x16 pmul inv rnd sat p a c k tsu XY-bank 1 AGU tsu XY-bank 2 AGU 16x16 pmul inv sat rnd pointer regs FFT bfly ARC 600 290 MHz worst-case 0.13um ASIC process Dimensions: 1.05mm x 1.87mm (2 sq.mm) • Challenge: • 50% higher clock frequency • 25% lower power consumption • 6 months, team of 4 (grew to 30 during verification) • Results: • Again completed on time • Announced MPF’03 (Oct’03) • All performance targets met • Novelty: • I-cache power saving techniques • Static branch prediction (inherently low power) • Coded for power-aware and physically-aware synthesis • 40 W / MHz power consumption (CPU) Team Talent Review - Nigel Topham

6. Research interests • Mixture of Deeply Technical + Methodology issues • Micro-architecture • Low power (new techniques) • High performance (for low-power embedded systems) • Energy aware, adaptive micro-architecture • What are the 5-10 yr challenges? • Compiler optimisation • Compiler / architecture synergy – working together is better • Energy aware compilation – existing systems v.inefficient • High-performance embedded systems • Configurable computing • NRE cost mandates flexibility in most scenarios • System-on-chip design • IP is expensive to produce, doubtful business model in isolation • Rarely trusted (re-verification problem) • How can eScience help? Team Talent Review - Nigel Topham

7. ICSA research summary • Optimising compilers (Mike O’Boyle) • High-level restructuring • Iterative and adaptive compilation • QCD architecture simulation (Roland Ibbett, Tony Kennedy) • Design space exploration through architecture simulation • Hardware/software co-simulation for performance prediction • Speckled computing (Arvind) • Similar to Smart Dust concept • Scottish university consortium to develop demonstrators • Parallel computing • Structured parallelism (Murray Cole) • Compiler/architecture support for cellular multi-processors - (IBM, Marcelo Cintra) • New EU Network of Excellence (almost) announced • High Performance Embedded Architecture and Compilation • ICSA is UK coordinator Team Talent Review - Nigel Topham