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Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation

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Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation

Keheng Huang1,2, Yu Hu1, and Xiaowei Li1

1Key Laboratory of Computer System and ArchitectureInstitute of Computing Technology Chinese Academy of Sciences

2Graduate University of Chinese Academy of Sciences

- Background
- Motivation
- Cross-layer optimized placement and routing
- Experimental results
- Conclusions

- Architecture of SRAM-based FPGAs

- Architecture of SRAM-based FPGAs

Segments

- Architecture of SRAM-based FPGAs

Segments

- Architecture of SRAM-based FPGAs
- Configuration bits (>98% of all SRAM bits)
- Routing resources (80% of configuration bits)

- User bits (<2% of all SRAM bits)

- Configuration bits (>98% of all SRAM bits)

Segments

- The reliability of routing resources needs to be seriously considered during placement and routing

Design specification

- Application design level

- Physical design level

Synthesis

and mapping

- RoRA[TC’06]
- TMR designs only

Gate-level netlist

- SEU-Aware P & R[ISQED’07]
- Dimensions of bounding box

- SEU-Aware Router [DAC’07]
- Number of configuration bits

Placement

and routing

- Reliability-aware P & R[ITC’10]
- Dimensions of bounding box

Bit Stream

SER

evaluation criterion

Application level factor

(EPP)

Propagation probability

+

Physical level factor

- (Node error rate)

Occurrence probability

Prior P& R guidance criterion

SER

evaluation criterion

Application level factor

(EPP)

All EPPs are equal?

+

Estimated SER

Physical level factor

- (Node error rate)

Physical level factor

(Bounding boxes, Configuration bits)

- Application level factor (EPPs) varies significantly

- Application level factor (EPPs) varies significantly

- Overview

- Overview

- Overview

- Overview

- Overview

- Overview

- Error propagation probability (EPP)
- Monte Carlo simulation
- Test vectors (high accuracy)
- Traverse the design N times (high complexity)

- Static analysis
- Signal probability and error propagation rules
(lower accuracy)

- Traverse the design twice per fault
(lower complexity)

- Signal probability and error propagation rules

- Monte Carlo simulation

- Error propagation probability (EPP)
- Monte Carlo simulation
- Test vectors (high accuracy)
- Traverse the design N times (high complexity)

- Static analysis
- Signal probability and error propagation rules
(lower accuracy)

- Traverse the design twice per fault
(lower complexity)

- Signal probability and error propagation rules

- Monte Carlo simulation

- A method with high accuracy and low complexity?

- Besides 0 and 1, “X” bit is introduced
- Introduce the cube and cover in logic synthesis
- Covers adjoin V:(set union:∪)
- Covers interface I:(set intersection: ∩)

0XX = {000,001,010,011}

cube

cover ={0XX, 1XX}

adjoin :{00X} V {01X} = {0XX}

interface: {00X} I {001} = {001}

- Forward traverse: compute the vectors that set the logic of the wire as 0 and 1 respectively

- Forward traverse: compute the vectors that set the logic of the wire as 0 and 1 respectively

- Forward traverse: compute the vectors that set the logic of the wire as 0 and 1 respectively
- Backward traverse: compute the vectors that can propagate the fault to outputs

- Forward traverse: compute the vectors that set the logic of the wire as 0 and 1 respectively
- Backward traverse: compute the vectors that can propagate the fault to outputs

- Error propagation probability (EPP)
- Compare with traditional Monte Carlo simulation
- For each fault, traverse the design N times

Ncare-cover: number of vectors stored in care-cover

Ninputs: total number of input vectors

- Comparison of computational complexity
- N: number of input vectors
- V: number of LUTs
- E: number of interconnecting wires
- g: number of configuration bits per LUT or wire
- Cavg: average compression ratio of all covers

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost

- Finer granularity estimate of SER

- Finer granularity estimate of SER

- Finer granularity estimate of SER

- Finer granularity estimate of SER

- Finer granularity estimate of SER

- Finer granularity estimate of SER

MCNC benchmark set

- Berkeley ABC mapper

Logic resources:

4 6-input LUTs per CLB

Routing channel width:

30% increase

Gate-level netlist

- VPR: Academic FPGA placement and routing tool

Bit Stream

- Comparison of EPP accuracy and run time
- Monte Carlo simulation
- DCOW: partial Monte Carlo simulation
- Cube-based EPP analysis

- Comparison of SER mitigation
- Original VPR
- Guided by physical level factor only (PPL)
- Cross-layer optimized placement and routing algorithm (COPAR)

- Monte Carlo simulation (golden model)
- DCOW: partial Monte Carlo simulation (DAC’10)
- Cube-based analysis (our method)

Ncube: number of test vectors computed by cube-based analysis

Nsim: number of test vectors computed by Monte Carlo simulation

Ninputs: total number of input vectors

Comparison of EPP Accuracy and Run Time

Comparison of EPP Accuracy and Run Time

Comparison of EPP Accuracy and Run Time

100%

93.53%

85.61%

- Observe the gap between the SER evaluation criterion and guidance criterion for soft error mitigation (gini coefficient=0.646)
- Introduce cube-based EPP analysis to compute the application level factor (gap<1%)
- Propose a cross-layer optimized placement and routing algorithm (SER mitigation>14%)

- Thank You for Your Attention
- Question?