Cross layer optimized placement and routing for fpga soft error mitigation
Download
1 / 49

Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation - PowerPoint PPT Presentation


  • 102 Views
  • Uploaded on

Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation. Keheng Huang 1,2 , Yu Hu 1 , and Xiaowei Li 1 1 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences 2 Graduate University of Chinese Academy of Sciences.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation' - fuller


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Cross layer optimized placement and routing for fpga soft error mitigation

Cross-layer Optimized Placement and Routing for FPGA Soft Error Mitigation

Keheng Huang1,2, Yu Hu1, and Xiaowei Li1

1Key Laboratory of Computer System and ArchitectureInstitute of Computing Technology Chinese Academy of Sciences

2Graduate University of Chinese Academy of Sciences


Outline
Outline Error Mitigation

  • Background

  • Motivation

  • Cross-layer optimized placement and routing

  • Experimental results

  • Conclusions


Background
Background Error Mitigation

  • Architecture of SRAM-based FPGAs


Background1
Background Error Mitigation

  • Architecture of SRAM-based FPGAs

Segments


Background2
Background Error Mitigation

  • Architecture of SRAM-based FPGAs

Segments


Background3
Background Error Mitigation

  • Architecture of SRAM-based FPGAs

    • Configuration bits (>98% of all SRAM bits)

      • Routing resources (80% of configuration bits)

    • User bits (<2% of all SRAM bits)

Segments

  • The reliability of routing resources needs to be seriously considered during placement and routing


Reliability oriented eda flow
Reliability Oriented EDA Flow Error Mitigation

Design specification

  • Application design level

  • Physical design level

Synthesis

and mapping

  • RoRA[TC’06]

  • TMR designs only

Gate-level netlist

  • SEU-Aware P & R[ISQED’07]

  • Dimensions of bounding box

  • SEU-Aware Router [DAC’07]

  • Number of configuration bits

Placement

and routing

  • Reliability-aware P & R[ITC’10]

  • Dimensions of bounding box

Bit Stream


Soft error rate ser
Soft Error Rate (SER) Error Mitigation

SER

evaluation criterion

Application level factor

(EPP)

Propagation probability

+

Physical level factor

  • (Node error rate)

Occurrence probability


Key observation
Key Observation Error Mitigation

Prior P& R guidance criterion

SER

evaluation criterion

Application level factor

(EPP)

All EPPs are equal?

+

Estimated SER

Physical level factor

  • (Node error rate)

Physical level factor

(Bounding boxes, Configuration bits)


Key observation1
Key Observation Error Mitigation

  • Application level factor (EPPs) varies significantly


Key observation2
Key Observation Error Mitigation

  • Application level factor (EPPs) varies significantly








Cube based epp analysis
Cube-based EPP Analysis Error Mitigation

  • Error propagation probability (EPP)

    • Monte Carlo simulation

      • Test vectors (high accuracy)

      • Traverse the design N times (high complexity)

    • Static analysis

      • Signal probability and error propagation rules

        (lower accuracy)

      • Traverse the design twice per fault

        (lower complexity)


Cube based epp analysis1
Cube-based EPP Analysis Error Mitigation

  • Error propagation probability (EPP)

    • Monte Carlo simulation

      • Test vectors (high accuracy)

      • Traverse the design N times (high complexity)

    • Static analysis

      • Signal probability and error propagation rules

        (lower accuracy)

      • Traverse the design twice per fault

        (lower complexity)

  • A method with high accuracy and low complexity?


Cube based epp analysis2
Cube-based EPP Analysis Error Mitigation

  • Besides 0 and 1, “X” bit is introduced

  • Introduce the cube and cover in logic synthesis

  • Covers adjoin V:(set union:∪)

  • Covers interface I:(set intersection: ∩)

0XX = {000,001,010,011}

cube

cover ={0XX, 1XX}

adjoin :{00X} V {01X} = {0XX}

interface: {00X} I {001} = {001}


Cube based epp analysis3
Cube-based EPP Analysis Error Mitigation

  • Forward traverse: compute the vectors that set the logic of the wire as 0 and 1 respectively


Cube based epp analysis4
Cube-based EPP Analysis Error Mitigation

  • Forward traverse: compute the vectors that set the logic of the wire as 0 and 1 respectively


Cube based epp analysis5
Cube-based EPP Analysis Error Mitigation

  • Forward traverse: compute the vectors that set the logic of the wire as 0 and 1 respectively

  • Backward traverse: compute the vectors that can propagate the fault to outputs


Cube based epp analysis6
Cube-based EPP Analysis Error Mitigation

  • Forward traverse: compute the vectors that set the logic of the wire as 0 and 1 respectively

  • Backward traverse: compute the vectors that can propagate the fault to outputs


Application level factor
Application level factor Error Mitigation

  • Error propagation probability (EPP)

  • Compare with traditional Monte Carlo simulation

    • For each fault, traverse the design N times

Ncare-cover: number of vectors stored in care-cover

Ninputs: total number of input vectors


Application level factor1
Application level factor Error Mitigation

  • Comparison of computational complexity

    • N: number of input vectors

    • V: number of LUTs

    • E: number of interconnecting wires

    • g: number of configuration bits per LUT or wire

    • Cavg: average compression ratio of all covers


Cross layer optimized placement
Cross-layer Optimized Placement Error Mitigation

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost


Cross layer optimized placement1
Cross-layer Optimized Placement Error Mitigation

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost


Cross layer optimized placement2
Cross-layer Optimized Placement Error Mitigation

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost


Cross layer optimized placement3
Cross-layer Optimized Placement Error Mitigation

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost


Cross layer optimized placement4
Cross-layer Optimized Placement Error Mitigation

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost


Cross layer optimized placement5
Cross-layer Optimized Placement Error Mitigation

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost


Cross layer optimized placement6
Cross-layer Optimized Placement Error Mitigation

Total cost=a*timing cost + b*congestion cost + c*SER cost

SER cost= Phy cost * App cost


Cross layer optimized routing
Cross-layer Optimized Routing Error Mitigation

  • Finer granularity estimate of SER


Cross layer optimized routing1
Cross-layer Optimized Routing Error Mitigation

  • Finer granularity estimate of SER


Cross layer optimized routing2
Cross-layer Optimized Routing Error Mitigation

  • Finer granularity estimate of SER


Cross layer optimized routing3
Cross-layer Optimized Routing Error Mitigation

  • Finer granularity estimate of SER


Cross layer optimized routing4
Cross-layer Optimized Routing Error Mitigation

  • Finer granularity estimate of SER


Cross layer optimized routing5
Cross-layer Optimized Routing Error Mitigation

  • Finer granularity estimate of SER


Experimental setup
Experimental Setup Error Mitigation

MCNC benchmark set

  • Berkeley ABC mapper

Logic resources:

4 6-input LUTs per CLB

Routing channel width:

30% increase

Gate-level netlist

  • VPR: Academic FPGA placement and routing tool

Bit Stream


Experimental results
Experimental results Error Mitigation

  • Comparison of EPP accuracy and run time

    • Monte Carlo simulation

    • DCOW: partial Monte Carlo simulation

    • Cube-based EPP analysis

  • Comparison of SER mitigation

    • Original VPR

    • Guided by physical level factor only (PPL)

    • Cross-layer optimized placement and routing algorithm (COPAR)


Comparison of epp accuracy and run time
Comparison of EPP Accuracy and Run Time Error Mitigation

  • Monte Carlo simulation (golden model)

  • DCOW: partial Monte Carlo simulation (DAC’10)

  • Cube-based analysis (our method)

Ncube: number of test vectors computed by cube-based analysis

Nsim: number of test vectors computed by Monte Carlo simulation

Ninputs: total number of input vectors






Comparison of ser mitigation1
Comparison of SER Mitigation Error Mitigation

100%

93.53%

85.61%


Conclusions
Conclusions Error Mitigation

  • Observe the gap between the SER evaluation criterion and guidance criterion for soft error mitigation (gini coefficient=0.646)

  • Introduce cube-based EPP analysis to compute the application level factor (gap<1%)

  • Propose a cross-layer optimized placement and routing algorithm (SER mitigation>14%)



ad