Optimizing CASPER Designs using Xilinx PlanAhead

1. Optimizing CASPER Designs using Xilinx PlanAhead Kaushal Buch (Giant Metrewave Radio Telescope) & Mayur Deshmukh (A.E, CoreEl Technologies(I) Pvt Ltd)

2. Outline • Need of PlanAhead in CASPER Designs • PlanAhead Tool Solution • Case Study : Packetized Design(F-Engine) • Future Scope

3. Need for PlanAhead in CASPER designs • In general, PlanAhead tool is used in design optimization – with focus on performance, area and power. • Area optimization in CASPER design can help addition of auxiliary processing and test blocks like RFI mitigation, digital noise source etc. • Addressing power optimization using PlanAhead for sparsely populated CASPER designs. Note: PlanAhead is a feature available in Xilinx ISE.

4. PlanAhead Tool Solution • Interactive design and analysis • Timing, connectivity, resources, constraints • Detect design problems early • RTL development and analysis • Elaboration and exploration • Synthesis and implementation • Experiment with various strategies • Debugging with the ChipScope™ Pro tool • Interactive debug core insertion • Core implementation and management • I/O pin planning • Interactive rule-based I/O assignment • Analysis and floor planning • Timing, connectivity, resources • Analyze implementation results • Project Navigator integration • Used for analysis, I/O, and area constraints

5. Case Study: Packetized Design (F-Engine) Design Description: F-Engine of Packetized correlator is a 2 channel(single antenna, dual polarization) design with coarse delay, PFB, 512 channel FFT, Fine delay and fringe stop and 10GbE packetization blocks

6. Case Study: Packetized Design (F-Engine) Before Floorplanning After Floorplanning This is the space for the device view of original design Power consumption of Packetized design is 7.71mW and after floor planning it was observed to be 3.35mW

7. Case Study: Packetized Design (F-Engine) • Device capacity can be improved by compressing the logic with P blocks that are not timing critical. • Use the PlanAhead tool to implement your design, and then shrink the P block to a size just sufficient for the logic. This will pack the logic as tightly as possible to free up device resources for other more timing-critical P blocks. • Blocks that are not timing critical, and are not heavily connected to other parts of the design, are also good candidates for this technique.

8. Case Study: Packetized Design (F-Engine) Before I/O planning Before I/O planning This is the space for the Package view of original design

9. Future Scope • Exploring the following features of PlanAhead for optimization of CASPER designs : • Timing Analysis • Synthesis Optimization • I/O Planning • Floor planning • Partial Reconfiguration GMRT and CoreEl Technologies will collectively bring up PlanAhead tutorials for the benefit of CASPER community!

10. References • PlanAHead User Guide http://www.xilinx.com/support/documentation/dt_planahead_planahead11-1_userguides.htm PlanAHead Documentation http://www.xilinx.com/support/documentation/dt_planahead_planahead11-1.htm

11. Contact Information Kaushal Buch(Giant Metrewave Radio Telescope) Email: kdbuch@gmrt.ncra.tifr.res.in Mayur Deshmukh(Application Engineer, CoreEl Technologies) Email: mayur.deshmukh@coreel.com

12. TOWARDS A GREENER CASPER !