Cache Interference

1. Cache Interference • Multi-threaded architecture causing interference among threads (inter-thread misses) and increasing the interferences inside threads (intra-thread misses) • Could cause more than 20% of all the cache accesses into misses

2. Multi-Ported Cache • Would be the ideal option • But too expensive and complex to implement in terms of area and power (to which extend?)

3. Alternative solution • Bank Prediction • The bank information is available early in the pipeline before instruction scheduling • Thus, scheduling can be performed in a way that efficiently utilize the multiple bank structure

4. Instruction Cache • For instruction fetch, if the PC of different threads point to the same bank, then bank conflict occurs, we can only fetch one thread from one bank at a time, which means we can not achieve the anticipated fetch bandwidth • Then we do prediction to avoid this situation

5. Data Cache • Memory operations (load/store) predicted to access the same bank are not dispatched simultaneously • Thus save the resources otherwise wasted

6. Bank Predictor • Bank predictor can be based on bank history information, control flow information, and/or load target-address information • An address predictor is obviously extremely well suited to be adapted for bank prediction, since the bank is solely based on the load’s effective address

7. Performance aspect • The effectiveness of bank predictor is greatly influenced by the machine configuration and related penalties. • Two aspect • Prediction rate • Prediction accuracy