Cognitive radio kit framework experimental platform for dynamic spectrum research
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Cognitive Radio Kit Framework : Experimental Platform for Dynamic Spectrum Research . Ivan Seskar Rutgers, The State University of New Jersey www.winlab.rutgers.edu Contact: Ivan Seskar, Associate Director s eskar (at) winlab (dot) rutgers (dot) edu.

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Cognitive Radio Kit Framework : Experimental Platform for Dynamic Spectrum Research

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Cognitive radio kit framework experimental platform for dynamic spectrum research

Cognitive Radio Kit Framework : Experimental Platform for Dynamic Spectrum Research

Ivan Seskar

Rutgers, The State University of New Jersey

www.winlab.rutgers.edu

Contact: Ivan Seskar, Associate Director

seskar (at) winlab (dot) rutgers (dot) edu


Cognitive radio cr p latforms

Cognitive Radio (CR) platforms

  • Research community already has a variety of platforms for CR research

Microsoft Sora

USRP2

USRP

MIT Airblue

U. Of Colorado

RICE WARP Platform


Cognitive radio platform issues

Cognitive Radio platform issues

  • Problems with existing (experimental) platforms: do we wait for Moore’s law to catch up or we need new hardware architectures for CR?

    • “Analog” issues: range (frequency, power), agility, cost, scalability, future proofing

    • “Digital” issues: scalability, power consumption, performance vs. flexibility, cost, future proofing

    • Ease of “use” issues: how do we program/control these platforms?

  • Large scale experiments in realistic environments

    • Nation-wide (experimental) cognitive radio spectrum allocation

    • Multiple testbeds with different objectives

    • GENI advanced technology demonstrator of cognitive radio networks

  • Address New Application Needs

    • Spectrum sensing, vehicular networking


Spiral ii geni project cr kit

Spiral II GENI project: CR kit

  • Range of baseband FPGA platforms

  • 4 (2) configurable radio modules for phased or smart antenna applications with

    • Phase I: Each module allows two 25 MHz bands from 300 to 6000 MHz

    • Phase II: Each module allows two different 300 MHz bands from 100 to 7500 MHz

  • Each module supports independent full duplex operation.

  • 1 usec RF frequency switching time

  • Switched antenna diversity for both TX and RX channels.n

Wide-tuning Digital Radio (WDR) block diagram


Why crkit framework

Why CRKIT Framework ?

INNOVATIONCYCLE

  • Focus on Creativity, not Engineering Complexity :

  • Split Baseband in twodomain spaces :

    • Dynamic – Swappable Communication APPs

      • (creative problem)

    • Static - Open-sourced System-on-Chip

    • (complex engineering problem)

Focus on APP Development

NOT complete Radio

Abstract lower level design complexities from Users

  • FSoC Features

  • Access to lower level resources thru APIs

  • VITA radio transport protocol for radio control

  • Networking capable node

  • Support up to four dynamic APPs

  • Library of Open-sourced Communication APPs

  • Static Framework utilization level < 15% for V5SX95, even less for newer technologies, for ex. Virtex7 .

  • Transparent to underlying FPGA technology.

  • Can be ported to future HW platforms and newer FPGA technologies.

  • Build Radio :

  • Non trivial effort

  • Substantial barrier to entry

  • Many engineering man-hours needed

  • Requires cross-disciplinary expertise

Live system runs

CRKIT= make real-time and wide-tuning radio a viable solution for large scale experiments.

WDR from Radio Technology Solutions


Crkit framework overview

CRKIT Framework Overview

CRKIT

HW

Platform

SW

Platform

ORBIT

Integration

Wide-tuning

Radio

Flexible

Baseband

Embedded

HOST

PHY

Layer Exp.

Exp.

Scalability

FPGA-

SoC

Comm.

APPs

Radio

APIs

OMF

  • Baseband Processor :

  • FPGA-based off-the-shelf board

  • Multitude of high-speed IOs : GigE, USB, PCIe

  • Control up to 4 full-duplex wideband radios

  • FPGA-based System-on-Chip (FSoC) implementation

  • Wide-tuning Radio (WDR) Module :

  • Wide-tuning range : 100MHz to 7.5GHz

  • 36MHz bandwidth

  • 50Msps 12-bit ADC, 200Msps 12-bit DAC

  • 1us switch between frequencies


Fpga soc overview

FPGA SoC Overview

  • FPGA SoC components :

    • Ethernet Port (static)

      • Gigabit Ethernet rate

      • frame synchronization

      • frame generation/formatting

    • Packet Processor (static)

      • packet classification/forwarding

      • Control packets -> Processor Core

      • Data packets -> APP

      • Memory management for APP data

      • IP/VITA packet generation/formatting

    • Application (dynamic)

      • User specific designs e.g. simple QPSK/QAM, OFDM, FHSS, DSSS…

      • Support up to 4 APPs simultaneously

      • Swappable APPs, can either reside in RAM or downloadable through Ethernet port.

    • RF Port (static)

      • interfacing to DA/AD

    • RMAP Processor (static)

      • Sub-system interfacing and control

      • Address decoding

      • RF SPI Control

    • Processor Core (static)

      • 32-bit Softcore processor

      • bus interconnect

      • interfacing to 32MB DRAM

      • interfacing to 16MB FLASH

Three distinct data flows through system:

1) APP/Processor Core to outbound ethernet port

2) Inbound ethernet port to APP

3) Inbound ethernet port to Processor Core


Crkit transport layers

CRKIT Transport Layers

APP domain (dynamic)

Framework Domain :

  • ETH Layer – Ethernet Physical layer only, no MAC. Only Ethernet frames with Broadcast MAC or matching destination MAC addresses are forwarded to IP layer.

  • IP Layer (Fast Path) –

    • Hardware based implementation

    • Only a subset of IP and UDP functions.

    • Fast track is reserved for APP data related traffic

    • Data IP packets are routed to the fast track based on specific UDP port number.

  • IP Layer (Slow Path) –

    • Software based implementation

    • Support TCP as this is done in SW e.g. processor core.

    • Slow track is reserved mostly for control related traffic : CRKit hardware configuration (register map access) and RF control.

    • Any IP packets with UDP port number not matching the fast track UDP port number will be routed to the slow track.

  • Note : for Address Resolution Protocol (ARP) the IP layer is bypassed, we parse the packets based on Ethernet frame Ethertype field.

  • VRT Layer –

    • VITA Radio Transport layer, only a subset of VITA standard is supported.

    • VRT layer is optional, bypass this layer if not used.

    • VRT useful to mux multiple radio streams to a single pipe, and demux at the other end.

    • Standardized radio packet types: 1) Data for signal data transmission, could be digitized I/Q samples. 2) Context for control information such as set frequency, power level, bandwidth and so forth.

Framework domain (static)

Application Domain :

  • User Specific Layer - since we are in the APP domain, users have their freedom to add any new layers they may wish.

  • Wireless PHY – again user specific implementation.


Inbound data flow

Inbound Data Flow

PCORE CMD FORMAT

Ethertype = 0x0800 - IPv4

0x0806 - ARP

If (V==1) then

VITA context packet

Else

non-VITA packet

use ethertype field for further parsing

Endif;

Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM.

PortID Lookup

Table

  • Forward ethernet payload if :

  • incoming MAC = dMAC

  • incoming MAC = Broadcast

  • Append Ethertype field (16-bit) to ethernet payload

if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000-1004) then

forward UDP payload to VITA Receiver

else

forward packet to PCORE


Inbound register map

Inbound Register Map

For UDP Port 1000 Traffic

(VITA)

Registers visible to PCORE

For non-VITA traffic

UDP 1001 => P0

UDP 1002 => P1

UDP 1003 => P2

UDP 1004 => P3

StreamID lookup

(direct-mapped)

APP Identifier


Outbound data flow

Outbound Data Flow

If IP-Flag then IP packet processing.

Lookup using PortID

VRT Receiver

Lookup using PortID

if V-Flag then Enable VITA formatting


Outbound packet processor rmap

Outbound Packet Processor RMAP

VITA enable flag

IP enable flag

VITA header

IP header

Lookup using PID

Data/Context

Lookup using PID

StreamID Lookup Table

MAC/IP Lookup Table


Crkit register address map

CRKIT Register Address Map

Upper 4 MSBs :

0x0-0x1 : PCORE

0x2 : CRKIT

Others : Unused

0x0 : CMN

0x1 : ETH

0x2 : PKT

0x4-0xB : APP

0xC : DAC IF

0xD : ADC IF

INT

SPI, LED

DCM/CLOCK

CE


Crkit programming model

CRKIT Programming Model

Network

CRKIT

HOST

CRKIT

development

Application

development

Java, C#

C

C

GUI

Algorithm

Comm.

APP

Embedded

SW

System

Debugging

System

Test

CR

DSA

VHDL/

Verilog

Mathworks

Simulink

IP

Networking

HW

Configuration

Host

CMD Parsing

DHCP/ARP

Lookup Tables/

RF

ETH/VITA


App development flow

APP Development Flow

APP Specification

PCORE

boots

CRKIT

Flow

Design dynamic

APP

Execute CRKIT

Embedded SW

MATLAB Simulink Flow

APP Validation

  • Get IP address using DHCP

  • Discover HOST

  • Configure CRKIT hardware

  • Parse HOST commands

CRKIT

Embedded SW

Compile APP

Networking

Link APP to

Framework

HW

Config.

Host

CMD Parsing

initial

config.

Compile

Framework

Xilinx

ISE Flow

RF Control

Lookup Table

Configuration

Generate

FPGA bit file

dynamic

Config.

(ETH/VITA)

Download

to Hardware


Innovation cycle

Innovation Cycle

Feedback

idea

Algorithms/

Models

Build

Radio

Live

Experiments

Creative

Processes

Engineering Processes


App simulink environment

APP SimulinkEnvironment

Data

Verification

IO

Validation

Channel

Model

BMU

MON

APP

RF

LPBK

I/Q

data

.txt files

BMU

DRV

I/Q

ETH

.txt files

Register

Read/Write

PCORE

DRIVER

Send X data packets

CMD

.txt file


App simulink testbench

APP SimulinkTestbench


Rendezvous apps

Rendezvous APPs


Qpsk transmitter

QPSK Transmitter


Qpsk receiver

QPSK Receiver


Rendezvous app fpga utilization

Rendezvous APP – FPGA Utilization


Orbit integration

ORBIT Integration

Actual SB6 with two CRKITs

ORBIT SB6

OPEN TO ORBIT COMMUNITY !


Conclusion

Conclusion

  • CRKIT = Advanced Radio System enabling experimental research in CR and DSA techniques

  • Powerful combination of Wideband Radio and Flexible Baseband Processing

  • FSoC Static and Dynamic domain spaces

  • APP development for Creativity and Productivity => MATLAB/Simulink

  • Framework development for Engineering Complexity=> Traditional Hardware design flow

  • ORBIT Integration => User Friendliness Experience + Experimentation Scalability


Future work

Future Work

  • Extend APP library : OFDM-based waveform APP

  • Upgrade Static framework to support live loadable APPs from Network :

    • Clock Management

    • Run-time Reconfiguration

  • Port Linux to PCORE

  • Integrate CRKIT fully into ORBIT Management Framework (OMF)

  • Extreme Digital Radio (XDR) : 800MHz Bandwidth

  • Upgrade baseband processor board to newer and higher performance FPGA technologies


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