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VHDL Refresher. Lecture 2. R equired reading. S. Brown and Z. Vranesic , Fundamentals of Digital Logic with VHDL Design Chapter 2.9, Introduction to CAD tools Chapter 2.10, Introduction to VHDL Chapter 4.12, Examples of Circuits Synthesized from VHDL Code

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vhdl refresher

VHDL Refresher

Lecture 2

ECE 448 – FPGA and ASIC Design with VHDL

r equired reading
Required reading
  • S. Brown and Z. Vranesic,Fundamentals of Digital Logic with VHDL Design
    • Chapter 2.9, Introduction to CAD tools
    • Chapter 2.10, Introduction to VHDL
    • Chapter 4.12, Examples of Circuits
    • Synthesized from VHDL Code
    • Chapter 5.5.3, Representation of Numbers in VHDL Code

ECE 448 – FPGA and ASIC Design with VHDL

recommended reading
Recommended reading
  • Sundar Rajan, Essential VHDL: RTL Synthesis
  • Done Right
  • Chapter 1, VHDL Fundamentals
  • Chapter 2, Getting Your First Design Done
  • (see errata at http://www.vahana.com/bugs.htm)

ECE 448 – FPGA and ASIC Design with VHDL

recommended reading1
Recommended reading
  • Wikipedia – The Free On-line Encyclopedia
  • VHDL - http://en.wikipedia.org/wiki/VHDL
  • Verilog - http://en.wikipedia.org/wiki/Verilog

ECE 448 – FPGA and ASIC Design with VHDL

r ecommended reading for next week
Recommended reading for next week

Material covered next week

and required during the first lab experiment

  • S. Brown and Z. Vranesic,Fundamentals of Digital Logic with VHDL Design
    • Chapter 6, Combinational-Circuit Building
    • Blocks
    • Chapter 5.5, Design of Arithmetic Circuits
    • Using CAD Tools

ECE 448 – FPGA and ASIC Design with VHDL

slide6

Brief History of VHDL

ECE 448 – FPGA and ASIC Design with VHDL

slide7
VHDL
  • VHDL is a language for describing digital hardware used by industry worldwide
    • VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

ECE 448 – FPGA and ASIC Design with VHDL

genesis of vhdl
Genesis of VHDL

State of art circa 1980

  • Multiple design entry methods and

hardware description languages in use

  • No or limited portability of designs

between CAD tools from different vendors

  • Objective: shortening the time from a design concept to implementation from

18 months to 6 months

ECE 448 – FPGA and ASIC Design with VHDL

a brief history of vhdl
A Brief History of VHDL
  • June 1981: Woods Hole Workshop
  • July 1983: contract awarded to develop VHDL
    • Intermetrics
    • IBM
    • Texas Instruments
  • August 1985: VHDL Version 7.2 released
  • December 1987:

VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard

ECE 448 – FPGA and ASIC Design with VHDL

three versions of vhdl
Three versions of VHDL
  • VHDL-87
  • VHDL-93
  • VHDL-01
  • VHDL-06

ECE 448 – FPGA and ASIC Design with VHDL

slide11

Verilog

ECE 448 – FPGA and ASIC Design with VHDL

v erilog
Verilog
  • Essentially identical in function to VHDL
    • No generate statement
  • Simpler and syntactically different
    • C-like
  • Gateway Design Automation Co., 1985
  • Gateway acquired by Cadence in 1990
  • IEEE Standard 1364-1995
  • Early de facto standard for ASIC programming
  • Programming language interface to allow connection to non-Verilog code

ECE 448 – FPGA and ASIC Design with VHDL

vhdl vs verilog
VHDL vs. Verilog

ECE 448 – FPGA and ASIC Design with VHDL

slide14

How to learn Verilog by yourself ?

ECE 448 – FPGA and ASIC Design with VHDL

features of vhdl and verilog
Features of VHDL and Verilog
  • Technology/vendor independent
  • Portable
  • Reusable

ECE 448 – FPGA and ASIC Design with VHDL

slide16

VHDL for Synthesis

ECE 448 – FPGA and ASIC Design with VHDL

slide17

VHDL for Specification

VHDL for Simulation

VHDL for Synthesis

ECE 448 – FPGA and ASIC Design with VHDL

levels of design description
Levels of design description

Algorithmic level

Level of description

most suitable for synthesis

Register Transfer Level

Logic (gate) level

Circuit (transistor) level

Physical (layout) level

ECE 448 – FPGA and ASIC Design with VHDL

register transfer level rtl design description
Register Transfer Level (RTL) Design Description

Combinational

Logic

Combinational

Logic

Registers

ECE 448 – FPGA and ASIC Design with VHDL

slide20

VHDL Fundamentals

ECE 448 – FPGA and ASIC Design with VHDL

naming and labeling 1
Naming and Labeling (1)
  • VHDL is case insensitive

Example:

Names or labels

databus

Databus

DataBus

DATABUS

are all equivalent

ECE 448 – FPGA and ASIC Design with VHDL

naming and labeling 2
Naming and Labeling (2)

General rules of thumb (according to VHDL-87)

  • All names should start with an alphabet character (a-z or A-Z)
  • Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)
  • Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)
  • Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)
  • All names and labels in a given entity and architecture must be unique

ECE 448 – FPGA and ASIC Design with VHDL

valid or invalid
Valid or invalid?

7segment_display

A87372477424

Adder/Subtractor

/reset

And_or_gate

AND__OR__NOT

Kogge-Stone-Adder

Ripple&Carry_Adder

My adder

ECE 448 – FPGA and ASIC Design with VHDL

free format
Free Format
  • VHDL is a “free format” language

No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.

Example:

if (a=b) then

or

if (a=b) then

or

if (a =

b) then

are all equivalent

ECE 448 – FPGA and ASIC Design with VHDL

readability standards
Readability standards

ESA VHDL Modelling Guidelines

published by

European Space Research and Technology Center

in September 1994

available at the course web page

ECE 448 – FPGA and ASIC Design with VHDL

comments
Comments
  • Comments in VHDL are indicated with

a “double dash”, i.e., “--”

      • Comment indicator can be placed anywhere in the line
      • Any text that follows in the same line is treated as

a comment

      • Carriage return terminates a comment
      • No method for commenting a block extending over a couple of lines

Examples:

-- main subcircuit

Data_in <= Data_bus; -- reading data from the input FIFO

ECE 448 – FPGA and ASIC Design with VHDL

comments1
Comments
  • Explain Function of Module to Other Designers
  • Explanatory, Not Just Restatement of Code
  • Locate Close to Code Described
    • Put near executable code, not just in a header

ECE 448 – FPGA and ASIC Design with VHDL

slide28

Design Entity

ECE 448 – FPGA and ASIC Design with VHDL

design entity
Design Entity

design entity

entity declaration

architecture 1

architecture 2

architecture 3

Design Entity - most basic building block of a design.

One entity can have

many different architectures.

ECE 448 – FPGA and ASIC Design with VHDL

entity declaration
Entity Declaration

ENTITYnand_gateIS

PORT(

a : IN STD_LOGIC;

b : IN STD_LOGIC;

z : OUT STD_LOGIC

);

ENDnand_gate;

  • EntityDeclaration describes the interface of the component, i.e. input and output ports.

Entity name

Port type

Port names

Semicolon

No Semicolon

Reserved words

Port modes (data flow directions)

ECE 448 – FPGA and ASIC Design with VHDL

entity declaration simplified syntax
Entity declaration – simplified syntax

ENTITY entity_name IS

PORT (

port_name : signal_mode signal_type;

port_name : signal_mode signal_type;

………….

port_name : signal_mode signal_type);

END entity_name;

ECE 448 – FPGA and ASIC Design with VHDL

architecture
Architecture
  • Describes an implementation of a design entity
  • Architecture example:

ARCHITECTUREmodelOFnand_gateIS

BEGIN

z <= aNANDb;

ENDmodel;

ECE 448 – FPGA and ASIC Design with VHDL

architecture simplified syntax
Architecture – simplified syntax

ARCHITECTURE architecture_name OF entity_name IS

[ declarations ]

BEGIN

code

END architecture_name;

ECE 448 – FPGA and ASIC Design with VHDL

entity declaration architecture
Entity Declaration & Architecture

nand_gate.vhd

LIBRARY ieee;

USEieee.std_logic_1164.all;

ENTITYnand_gateIS

PORT(

a : IN STD_LOGIC;

b : IN STD_LOGIC;

z : OUT STD_LOGIC);

ENDnand_gate;

ARCHITECTURE dataflow OFnand_gateIS

BEGIN

z <= aNANDb;

END dataflow;

ECE 448 – FPGA and ASIC Design with VHDL

slide35

Tips & Hints

Place each entity in a different file.

The name of each file should be exactly the same

as the name of an entity it contains.

These rules are not enforced by all tools

but are worth following in order to increase

readability and portability of your designs

ECE 448 – FPGA and ASIC Design with VHDL

slide36

Tips & Hints

Place the declaration of each port,

signal, constant, and variable

in a separate line

These rules are not enforced by all tools

but are worth following in order to increase

readability and portability of your designs

ECE 448 – FPGA and ASIC Design with VHDL

mode in
Mode In

Port signal

Entity

a

Driver resides

outside the entity

ECE 448 – FPGA and ASIC Design with VHDL

mode out
Mode out

Entity

Port signal

Can’t read out

within an entity

Driver resides

inside the entity

z

c

c <= z

ECE 448 – FPGA and ASIC Design with VHDL

mode out with signal
Mode out with signal

Entity

Port signal

Driver resides

inside the entity

z

x

c

Signal X can be

read inside the entity

z <= x

c <= x

ECE 448 – FPGA and ASIC Design with VHDL

mode buffer
Mode buffer

Entity

Port signal

Driver resides

inside the entity

z

c

Port signal Z can be

read inside the entity

c <= z

ECE 448 – FPGA and ASIC Design with VHDL

mode inout
Mode inout

Entity

Port signal

a

Signal can be

read inside the entity

Driver may reside

both inside and outside

of the entity

ECE 448 – FPGA and ASIC Design with VHDL

port modes summary
Port Modes - Summary

The Port Mode of the interface describes the direction in which data travels with respect to the component

  • In: Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.
  • Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.
  • Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.
  • Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator

ECE 448 – FPGA and ASIC Design with VHDL

slide43

Libraries

ECE 448 – FPGA and ASIC Design with VHDL

library declarations
Library declarations

Library declaration

Use all definitions from the package

std_logic_1164

LIBRARY ieee;

USEieee.std_logic_1164.all;

ENTITYnand_gateIS

PORT(

a : IN STD_LOGIC;

b : IN STD_LOGIC;

z : OUT STD_LOGIC);

ENDnand_gate;

ARCHITECTURE dataflow OFnand_gateIS

BEGIN

z <= aNANDb;

END dataflow;

ECE 448 – FPGA and ASIC Design with VHDL

library declarations syntax
Library declarations - syntax

LIBRARY library_name;

USE library_name.package_name.package_parts;

ECE 448 – FPGA and ASIC Design with VHDL

fundamental parts of a library
Fundamental parts of a library

LIBRARY

PACKAGE 1

PACKAGE 2

TYPES

CONSTANTS

FUNCTIONS

PROCEDURES

COMPONENTS

TYPES

CONSTANTS

FUNCTIONS

PROCEDURES

COMPONENTS

ECE 448 – FPGA and ASIC Design with VHDL

libraries
Libraries
  • ieee
  • std
  • work

Need to be explicitly

declared

Specifies multi-level logic system,

including STD_LOGIC, and

STD_LOGIC_VECTOR data types

Specifies pre-defined data types

(BIT, BOOLEAN, INTEGER, REAL,

SIGNED, UNSIGNED, etc.), arithmetic

operations, basic type conversion

functions, basic text i/o functions, etc.

Visible by default

Current designs after compilation

ECE 448 – FPGA and ASIC Design with VHDL

slide48

STD_LOGIC Demystified

ECE 448 – FPGA and ASIC Design with VHDL

s td logic
STD_LOGIC

LIBRARY ieee;

USEieee.std_logic_1164.all;

ENTITYnand_gateIS

PORT(

a : IN STD_LOGIC;

b : IN STD_LOGIC;

z : OUT STD_LOGIC);

ENDnand_gate;

ARCHITECTURE dataflow OFnand_gateIS

BEGIN

z <= aNANDb;

END dataflow;

What is STD_LOGIC you ask?

ECE 448 – FPGA and ASIC Design with VHDL

std logic type demystified
STD_LOGIC type demystified

ECE 448 – FPGA and ASIC Design with VHDL

more on std logic meanings 1
More on STD_LOGICMeanings (1)

‘1’

‘X’

Contention on the bus

X

‘0’

ECE 448 – FPGA and ASIC Design with VHDL

more on std logic meanings 2
More on STD_LOGICMeanings (2)

ECE 448 – FPGA and ASIC Design with VHDL

slide53

More on STD_LOGICMeanings (3)

‘H’

‘0’

VDD

VDD

‘1’

‘L’

ECE 448 – FPGA and ASIC Design with VHDL

more on std logic meanings 4
More on STD_LOGICMeanings (4)
  • Do not care.
  • Can be assigned to outputs for the case of invalid
  • inputs(may produce significant improvement in resource utilization after synthesis).
  • Use with caution
  • ‘1’ = ‘-’ give FALSE

‘-’

ECE 448 – FPGA and ASIC Design with VHDL

resolving logic levels
Resolving logic levels

X 0 1 Z W L H -

X X X X X X X X X

0 X 0 X 0 0 0 0 X

1 X X 1 1 1 1 1 X

Z X 0 1 Z W L H X

W X 0 1 W W W W X

L X 0 1 L W L W X

H X 0 1 H W W H X

- X X X X X X X X

ECE 448 – FPGA and ASIC Design with VHDL

slide56

Modeling Wires and Buses

ECE 448 – FPGA and ASIC Design with VHDL

signals
Signals

SIGNALa : STD_LOGIC;

SIGNALb : STD_LOGIC_VECTOR(7 DOWNTO 0);

a

1

wire

b

bus

8

ECE 448 – FPGA and ASIC Design with VHDL

standard logic vectors
Standard Logic Vectors

SIGNAL a: STD_LOGIC;

SIGNALb: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNALc: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNALd: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNALe: STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNALf: STD_LOGIC_VECTOR(8 DOWNTO 0);

……….

a <= ‘1’;

b <= ”0000”; -- Binary base assumed by default

c <= B”0000”; -- Binary base explicitly specified

d <= ”0110_0111”; -- You can use ‘_’ to increase readability

e <= X”AF67”; -- Hexadecimal base

f <= O”723”; -- Octal base

ECE 448 – FPGA and ASIC Design with VHDL

vectors and concatenation
Vectors and Concatenation

SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNALb: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNALc, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”;

b <= ”1111”;

c <= a & b; -- c = ”00001111”

d <= ‘0’ & ”0001111”; -- d <= ”00001111”

e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &

‘1’ & ‘1’;

-- e <= ”00001111”

ECE 448 – FPGA and ASIC Design with VHDL

fixed rotation in vhdl
Fixed Rotation in VHDL

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0);

A(3)

A(2)

A(1)

A(0)

A<<<1

A(2)

A(1)

A(0)

A(3)

ArotL <=

ECE 448 – FPGA and ASIC Design with VHDL

fixed shift in vhdl
Fixed Shift in VHDL

A(1)

A(0)

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);

A(3)

A(2)

A>>1

‘0’

A(3)

A(2)

A(1)

AshiftR <=

ECE 448 – FPGA and ASIC Design with VHDL

slide62

VHDL Design Styles

ECE 448 – FPGA and ASIC Design with VHDL

vhdl design styles
VHDL Design Styles

dataflow

VHDL Design

Styles

  • Testbenches

structural

behavioral

Components and

interconnects

Concurrent

statements

Sequential statements

  • Registers
  • State machines

Subset most suitable for synthesis

ECE 448 – FPGA and ASIC Design with VHDL

slide64

xor3 Example

ECE 448 – FPGA and ASIC Design with VHDL

entity xor3
Entity xor3

LIBRARYieee;

USEieee.std_logic_1164.all;

ENTITYxor3_gate IS

PORT(

A : IN STD_LOGIC;

B : IN STD_LOGIC;

C : IN STD_LOGIC;

Result : OUT STD_LOGIC

);

end xor3_gate;

ECE 448 – FPGA and ASIC Design with VHDL

dataflow architecture xor3 g ate
Dataflow Architecture (xor3 gate)

ARCHITECTUREdataflowOFxor3_gate IS

SIGNAL U1_OUT: STD_LOGIC;

BEGIN

U1_OUT<= A XORB;

Result <= U1_OUT XOR C;

ENDdataflow;

U1_OUT

ECE 448 – FPGA and ASIC Design with VHDL

dataflow description
Dataflow Description
  • Describes how data moves through the system and the various processing steps.
  • Data Flow uses series of concurrent statements to realize logic. Concurrent statements are evaluated at the same time; thus, order of these statements doesn’t matter.
  • Data Flow is most useful style when series of Boolean equations can represent a logic.

ECE 448 – FPGA and ASIC Design with VHDL

structural architecture xor3 gate
Structural Architecture (xor3 gate)

A

B

Result

xor3_gate

C

I1

I1

Y

Y

I2

I2

ARCHITECTUREstructuralOF xor3_gate IS

SIGNALU1_OUT:STD_LOGIC;

COMPONENT xor2

PORT(

I1 : IN STD_LOGIC;

I2 : IN STD_LOGIC;

Y : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

U1: xor2PORT MAP (I1 => A,

I2 => B,

Y => U1_OUT);

U2: xor2PORT MAP (I1 => U1_OUT,

I2 => C,

Y => Result);

ENDstructural;

U1_OUT

ECE 448 – FPGA and ASIC Design with VHDL

slide69
xor2

xor2.vhd

LIBRARY ieee;

USEieee.std_logic_1164.all;

ENTITY xor2 IS

PORT(

I1: IN STD_LOGIC;

I2: IN STD_LOGIC;

Y : OUT STD_LOGIC);

END xor2;

ARCHITECTURE dataflow OF xor2 IS

BEGIN

Y <= I1 xor I2;

END dataflow;

ECE 448 – FPGA and ASIC Design with VHDL

structural description
Structural Description
  • Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions.
  • Components are interconnected in a hierarchical manner.
  • Structural descriptions may connect simple gates or complex, abstract components.
  • Structural style is useful when expressing a design that is naturally composed of sub-blocks.

ECE 448 – FPGA and ASIC Design with VHDL

behavioral architecture xor3 gate
Behavioral Architecture (xor3 gate)

ARCHITECTUREbehavioralOF xor3IS

BEGIN

xor3_behave: PROCESS (A,B,C)

BEGIN

IF ((A XOR B XOR C) = \'1\') THEN

Result <= \'1\';

ELSE

Result <= \'0\';

END IF;

END PROCESSxor3_behave;

END behavioral;

ECE 448 – FPGA and ASIC Design with VHDL

behavioral description
Behavioral Description
  • It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works).
  • This style uses PROCESSstatementsin VHDL.

ECE 448 – FPGA and ASIC Design with VHDL

slide73
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ECE 448 – FPGA and ASIC Design with VHDL

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