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Testing for whole function. Previous To-Do. Add randomWait , UART into multiple rcvQ program Debug for sometimes sending twice in the same slot Caused by race condition of TBR, when checking valid time to send. Results.

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Presentation Transcript
previous to do
Previous To-Do
  • Add randomWait, UART into multiple rcvQprogram
  • Debug for sometimes sending twice in the same slot
    • Caused by race condition of TBR, when checking valid time to send
results
Results
  • In 18-minute experiment , the clock drift is smaller than the biggest value 80 us (@13 min) for last data slot in every minute
slide4
UART
  • Had dumped the UART information, but not correctly calculate now, need to revise
  • RX is receiving from parent while TX is send to children, need to combine two hop info. to get correct value
to do
To-Do
  • Get correct UART info to make sure whether crossing-slot problem occurs or not
  • Open CCA mechanism for CSMA to see the result
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