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OpenPET User Meeting: Status and Update

OpenPET User Meeting: Status and Update. Woon-Seng Choong, Jennifer Huber, William Moses, Qiyu Peng October 31, 2013.

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OpenPET User Meeting: Status and Update

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  1. OpenPET User Meeting: Status and Update Woon-Seng Choong, Jennifer Huber, William Moses, QiyuPeng October 31, 2013 This work is supported in part by the Director, Office of Science, Office of Biological and Environmental Research, Biological Systems Science Division of the U.S. Department of Energy under Contract No. DE-AC02-05CH1231and in part by the National Institutes of Health under grant R01 EB016104.

  2. Outline • Introduction • Detector Boards Status • Firmware and Software Status • Website Choong, IEEE NSS-MIC, October 31, 2013

  3. OpenPET Vision • Open Source • Hardware, Firmware, and Software • Schematics, Gerbers, BOM,… • Standardized Architecture • Compatible Alternate Hardware • Software Readily Transportable • Active User Community • Share Software and Expertise • Module, Calibration, DAQ, Display… OpenPET is the GATE ofNuclear Medical Imaging Electronics Choong, IEEE NSS-MIC, October 31, 2013

  4. OpenPET Hardware Architecture DetectorBoard SupportBoard Multiplexer Coincidence P P Detectors Host PC Data Control Choong, IEEE NSS-MIC, October 31, 2013

  5. Small System Host PC Detector Unit • 1 Support Crate, Up To 8Detector Boards • Up to 256 Analog Inputs (64 Block Detectors) • PC Interface Board Connects to PC Choong, IEEE NSS-MIC, October 31, 2013

  6. Standard System CU CI-1 CI-1 CI-1 MB-1 MB-1 MB-1 MB-1 MB-1 MB-1 MB-1 MB-1 Host PC … (up to eight) DU0 DU1 DU7 • Up To 8Detector Units, 1 Coincidence Units • Up to 2048 Analog Inputs (512 Block Detectors) • CoincidenceInterface Board Connects to CU Choong, IEEE NSS-MIC, October 31, 2013

  7. OpenPET Hardware Complete and available Detector Unit Support Board Complete and available Detector Board Detector Board Detector Board Detector Board Detector Board Detector Board Detector Board Detector Board Coincidence Interface Host PC Interface User IO Debugging 1 2 3 4 5 6 7 8 9 10 11 12 Power and Fans Minor revision in progress First version of 16-ch Detector Board has been fabricated and tested. Minor revision in progress. Under development Choong, IEEE NSS-MIC, October 31, 2013

  8. Support Crate 12-slot 6U VME 19” Rack Mountable Crate 96-pin VME Connectors Host PC Interface Board Power FPGAs User IO Board Debugging Board Fan Support Board 8 slots for Detector Boards • VME crate is available from Elma Electronics Inc. • Electronics boards are available from Terasic Technologies Choong, IEEE NSS-MIC, October 31, 2013

  9. Detector Boards • 16-Channel Detector Board • - A scaled-down version to provide working DB to the users. • - First version has been fabricated and tested. • - Minor design improvements and fixes are in progress. • - Final version to be available to users in a few months (early 2014). • 32-Channel Detector Board (based on conventional design) • - Design is almost complete. • - Layout and fabrication to start in a few months. • 32-Channel Detector Board (based on DRS4) • - Design to start next year. • - Expect to be available in 1-2 years. Choong, IEEE NSS-MIC, October 31, 2013

  10. 16-Channel Detector Board 2 MB Memory Only negative polarity inputs 96-pin VME Backplane Connector FPGA Altera Cyclone III Clock /Slice Out IN0 16-channel front-end circuitries IN1 Clock /Slice In . . . Data Digital I/O Singles Events IN14 Trigger IN15 Communication Bus (JTAG, SPI) Clock and Slice Power Control Lines Choong, IEEE NSS-MIC, October 31, 2013

  11. 16-Channel Detector Board x16 for each 16-ch Detector Board Filter 7MHz 12-bit ADC ADS5282 x-2 LTC6605-7 (+5V) OPA2694 (+/-5V) Slow Comparator SE to LVDS FPGA + IN - MAX964 Threshold Adjust (1 - 4000 mV) Fast Comparator Fast Amp PECL to LVDS x10 - + THS4303 (+/-2.5V) SY55855VKG MAX9602 OPA4227 Threshold Adjust (1-2500 mV) Choong, IEEE NSS-MIC, October 31, 2013

  12. 16-Channel Detector Board Logic Analyzer Connector Input Termination QUSB Connector 16-channel Timing Chain 2 MB SRAM FPGA (Cyclone III) 16-channel Energy Chain Power Regulator JTAG Connector AS Mode Connector Digital I/O External Clock Input ADC DIP Switch Choong, IEEE NSS-MIC, October 31, 2013

  13. 16-Ch DB Evaluation • 6.15 x 6.15 x 25 mm3 • LSO crystals R-9800 R-9800 Ge-68 17.0% fwhm 15.5% fwhm With high-performance electronics, energy resolution was 15.8% and 14.4%. Choong, IEEE NSS-MIC, October 31, 2013

  14. 16-Ch DB Evaluation • 6.15 x 6.15 x 25 mm3 • LaBr3 crystals R-9800 R-9800 Ge-68 7.8% fwhm 6.1% fwhm With high-performance electronics, energy resolution was 5.6% and 4.7%. => 16-Ch DB has good spectroscopic performance. Choong, IEEE NSS-MIC, October 31, 2013

  15. 16-Ch DB Evaluation • PET block detector: • 12x12 array of 4x4x22 mm3 LSO crystals, 4 Hamamatsu R-9800 PMTs Choong, IEEE NSS-MIC, October 31, 2013

  16. FPGA TDC 1) Low resolution (500 – 1000 ps LSB) - Based on multi-sampling. • Inputs are sent to four registers connected to four internal clocks (400 – 500 MHz) with 90° phase difference. • Easy to implement and takes less resources. 2) High resolution (25 – 50 ps LSB) - Based on delay chain and wave union. • Include auto calibration to compensate for temperature and power supply variation. • More complex to implement and takes more resources. References: • J. Wu, S. Hansen, and Z. Shi, “ADC and TDC implemented in using FPGA,” Proc. IEEE Nucl. Sci. Symp. Conf. Rec., Honolulu, HI, 2007, pp. 281–286. • J. Wu and Z. Shi, “The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay,” Proc. IEEE Nucl. Sci. Symp. Conf. Rec., Dresden, Germany, 2008, pp. 3440–3446. Choong, IEEE NSS-MIC, October 31, 2013

  17. Firmware/Software System calibration and characterization (control console and scripts) Acceptable range definition ? DAQ configuration and DAQ (scripts) System configuration and test (scripts) Data analysis and visualization (GUI and scripts) List mode data (with a header file) Data analysis reports List mode data (with a head file) System configuration files System HW/FW System HW/FW First Release Choong, IEEE NSS-MIC, October 31, 2013

  18. Firmware/Software (“Oscilloscope” Mode) Detector Board Support Board Host PC ADC Readout ADC Readout Event Transfer In Event Transfer Out Event Multiplexing Event Transfer Out Event Transfer In Event Multiplexing Event Transfer Out Event Transfer Out Event Processing Coincidence Processing Event Processing Coincidence Processing Event Transfer In Event Transfer In TimeStamp TDC Setup & Control Setup & Control Setup & Control Setup & Control Setup & Control Setup & Control Completed In Development Not Needed for Oscilloscope Mode • First Release: “Oscilloscope Mode” for Small System • Two Command Line Executables to Configure System and Acquire Data Choong, IEEE NSS-MIC, October 31, 2013

  19. Data Transfer Rate Via USB 2.0 Data rate (Million Bytes Per Second) • A maximum sustained data transfer rate of ~ 43 MB/s is achieved (theoretical maximum is 60 MB/s for USB 2.0) Choong, IEEE NSS-MIC, October 31, 2013

  20. Firmware / Software First Release • Necessary firmware on 16-Channel DB and SB to control the hardware and acquire list mode data via USB. - System configuration files to configure system. - List mode data is “Oscilloscope” mode. • Command line executable with arguments to control/configure the system. Ex., opet_cmd <arg1> <arg2> <arg3> … • Command line executableto acquire data in list mode. Ex., opet_acq <arg1> <arg2> <arg3> … • Currently under development and testing. • A major effort will go into documenting a User’s Guide before the first release. • Will be released when the 16-channel Detector Board is made available. Choong, IEEE NSS-MIC, October 31, 2013

  21. Website (openpet.lbl.gov) Choong, IEEE NSS-MIC, October 31, 2013

  22. Thank you for your attention

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