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Cascaded Counters

Cascaded Counters. Mod-N Counters. Generally we are interested in counters that count up to specific count values Not just powers of 2 A mod-N counter has N states Counts from 0 to N-1 then rolls over Requires flip flops For example… A 4-bit binary counter is a mod-16 counter

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Cascaded Counters

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  1. Cascaded Counters ECEn 224

  2. Mod-N Counters • Generally we are interested in counters that count up to specific count values • Not just powers of 2 • A mod-N counter has N states • Counts from 0 to N-1 then rolls over • Requires flip flops • For example… • A 4-bit binary counter is a mod-16 counter • A counter that counts from 0-9 is a mod-10 counter ECEn 224

  3. A Mod-4 CounterA.K.A. 2-bit counter CLR’•INC’ CLR 00 CLR’•INC CLR’•INC CLR’•INC’ CLR’•INC’ 11 01 CLR’•INC CLR’•INC 10 CLR’•INC’ ECEn 224

  4. A Mod-4 Counter With Rollover Signal CLR’•INC’ Mealy output CLR 00 CLR’•INC / RO CLR’•INC CLR’•INC’ CLR’•INC’ 11 01 CLR’•INC CLR’•INC 10 The ROLL signal is used to tell other circuitry that the counter is rolling over to all 0’s. CLR’•INC’ ECEn 224

  5. Cascaded Counters • Larger counters can be built by combining smaller counters together • The rollover signal is used to communicate when the upper counters should roll over • Two types of counters • Asynchronous • Synchronous ECEn 224

  6. clk clk 0 1 digit1 3 2 digit0 0 1 2 roll0 / clk1 Cascaded Asynchronous Counter digit1 digit0 2 clk1 Sequence should be: 00-01-02-03-10-11-12-… 2 clr clr Mod-4 Counter Mod-4 Counter But we get: 00-01-02-13-10-11-12-… As a general rule…. DO NOT tie the clock inputs on modules to anything but the clock! inc ‘1’ roll1 roll0 ECEn 224

  7. clk Cascaded Asynchronous Counter digit1 digit0 2 clk1 2 clr clr Mod-4 Counter Mod-4 Counter inc ‘1’ roll1 roll0 digit1 increments too early clk clr digit0 roll0 / clk1 digit1 ECEn 224

  8. Cascaded Asynchronous Counter • The more stages we add to the counter, the bigger the discrepancy between asynchronous counters and what we expect Stage 1 Expected Stage 2 Async Expected Stage 3 Async ECEn 224

  9. clk digit1 digit0 2 clk1 2 clr clr Mod4 Counter Mod4 Counter It is possible to modify the circuit to get the correct count sequence, but the roll signal must be glitch free! The transition from the value 1 to 2 (012 to 102) makes it difficult, if not impossible to eliminate glitches. inc ‘1’ roll1 roll0 clk 2 digit1 0 1 digit0 0 1 2 2 3 Possible hazard roll0 / clk1 ECEn 224

  10. Ripple Counters • When you tie a rollover-like signal to a clock on the next higher digit  ripple counter • A ripple counter is an asynchronous counter • Transitions are not all synchronized to the clock • Different flip flops change at different times • Similar to gated clocks (seen earlier) • Asynchronous circuits are an advanced topic ECEn 224

  11. Another Common Ripple Counter Q3 Q2 Q1 Q0 Counts in normal binary: 0000 0001 0010 0011 0100 0101 0110 0111 1000 … … T Q Q’ T Q Q’ T Q Q’ T Q Q’ ‘1’ ‘1’ ‘1’ ‘1’ CLK What’s wrong with this design? ECEn 224

  12. Timing Diagram clk Q0 changes in response to clock edge Only after Q0 changes does Q1’s FF get a clock Only after that does Q2’s FF get a clock Logic depending on Q3 has very little timeto react before next clock edge Net effect is that all the FF’s change at different times! Q0 Q1 Q2 Q3 ECEn 224

  13. Asynchronous and Ripple Counters • Because asynchronous and ripple counters are difficult to use correctly, they are avoided • Do not use them in your designs! • Violates globally synchronous design principle • Always use synchronous counters ECEn 224

  14. Synchronous Counters • In a synchronous counter, all flip flops are clocked by the same clock signal • They all change at the same time • Synchronous counters can be cascaded to create larger counters that are also globally synchronous ECEn 224

  15. A Mod-4 Counter Count Value D Q clr Terminal Count clk IFL D Q clk inc Roll Over ECEn 224

  16. A Mod-4 Counter Count Value D Q clr Terminal Count clk IFL D Q clk inc Roll Over We could make a mod-4 counter from the block shown in red. ECEn 224

  17. Cascaded Counters digit2[1:0] digit0[1:0] digit1[1:0] clk clr clr clr clr CV CV CV MOD4 MOD4 MOD4 TC TC TC inc inc inc inc ECEn 224

  18. Cascaded Counters digit2[1:0] digit0[1:0] digit1[1:0] clk clr clr clr clr CV CV CV Count Value MOD4 MOD4 MOD4 TC TC TC Terminal Count inc inc inc inc Rollover ECEn 224

  19. Cascaded Counters digit2[1:0] digit0[1:0] digit1[1:0] clk clr clr clr clr CV CV CV MOD4 MOD4 MOD4 TC TC TC inc inc inc inc Assume that the second timer is already at the terminal count. ECEn 224

  20. Cascaded Counters digit2[1:0] digit0[1:0] digit1[1:0] clk clr clr clr clr CV CV CV MOD4 MOD4 MOD4 TC TC TC inc inc inc inc ECEn 224

  21. Cascaded Counters digit2[1:0] digit0[1:0] digit1[1:0] clk clr clr clr clr CV CV CV MOD4 MOD4 MOD4 TC TC TC inc inc inc inc ECEn 224

  22. Cascaded Counters digit2[1:0] digit0[1:0] digit1[1:0] clk clr clr clr clr CV CV CV MOD4 MOD4 MOD4 TC TC TC inc inc inc inc ECEn 224

  23. Cascaded Counters digit2[1:0] digit0[1:0] digit1[1:0] clk clr clr clr clr CV CV CV MOD4 MOD4 MOD4 TC TC TC inc inc inc inc ECEn 224

  24. Cascaded Counters digit2[1:0] digit0[1:0] digit1[1:0] clk clr clr clr clr CV CV CV MOD4 MOD4 MOD4 TC TC TC inc inc inc inc ECEn 224

  25. Cascaded Counters digit2[1:0] digit0[1:0] digit1[1:0] clk clr clr clr clr CV CV CV MOD4 MOD4 MOD4 TC TC TC inc inc inc inc It looks like the inc signal ripples from counter to counter. How is this different from the ripple counter examples? ECEn 224

  26. Cascaded Synchronous Counter clk digit0 10 11 00 roll digit1 00 01 ECEn 224

  27. Cascaded Synchronous Counter • Notice that all signals are synchronized with the system clock roll0 roll1 clk digit0 digit1 digit2 Signals: ECEn 224

  28. A Mod-4 CounterWith consolidated rollover logic Count Value D Q clr Terminal Count clk IFL D Q Roll Over clk inc A good mod-4 counter includes the logic within the red block. ECEn 224

  29. A Mod-4 Counter inc dout MOD4 roll clk clr ECEn 224

  30. clk clk Cascading two Mod-4 Counters Count Sequence: digit1 digit0 Increment higher digit’s counter when lower digit’s counter is rolling over 0001020310111213202122233031323300 … digit1 digit0 2 2 dout dout clr clr MOD4 MOD4 clr clr inc roll0 roll1 inc roll inc roll ECEn 224

  31. clk clk clk Three-digit Mod-4 Counter • Can combine any counters that have a rollover signal to make larger counters • Combine two 16-bit counters to make a 32-bit counter • Combine three mod-4 counters to make a three-digit mod-4 counter digit2 digit1 digit0 2 2 2 dout dout dout clr clr clr MOD4 MOD4 MOD4 clr clr clr inc roll0 roll1 roll1 inc inc roll inc roll roll ECEn 224

  32. clk clk clk BCD Counter • Combine to create non-binary counters • BCD counter digit2 digit1 digit0 4 4 4 dout dout dout clr clr clr MOD10 MOD10 MOD10 clr clr clr inc roll0 roll1 roll1 inc inc roll inc roll roll ECEn 224

  33. clk clk clk Hybrid Counters • Can combine different kinds of mod counters • Combine an 8-bit counter with a 16-bit counter to create a 24-bit counter • Combine mod-24 and mod-60 counters to create a digital H:M:S clock Hours Minutes Seconds 5 6 6 dout dout dout clr clr clr MOD24 MOD60 MOD60 clr clr clr sec min day hour inc inc roll inc roll roll ECEn 224

  34. D Flip Flop with Asynchronous Clearand Clock Enable Clock Enable (a.k.a. Load) Clear (a.k.a. Reset) ECEn 224

  35. Mod-4 Counter D0 CLK CEO CE CE D1 ECEn 224

  36. Cascaded Synchronous Counter Digit0 Digit1 CEO CLK Reset Digit0 CEO Digit1 ECEn 224

  37. Library Counters • Component libraries often have several cascadable counters available • Can be cascaded to form desired width Xilinx Library Counters ECEn 224

  38. Summary • Mod-N counters are counters that count from 0 to N-1 then roll over • Adding rollover logic to counters allows us to cascade counters • We can build large counters from smaller ones • We can easily build non-binary counters • BCD counter • HMS clock counter • Always use synchronous counters instead of asynchronous counters ECEn 224

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