Ispd-2007

1. Ispd-2007 Repeater Insertion for Concurrent Setup and Hold Time Violations with Power-Delay Trade-Off Salim Chowdhury John Lillis Sun Microsystems University of Illinois at Chicago

2. Outline • Motivation • Modelling late & early modes concurrently • Identifying sub-optimal solutions in a list • The merging problem • Power-Delay Trade-Off • Interaction between late & early modes (examples) • Conclusions, limitations, and future directions • Acknowledgements

3. Motivation • Traditional Flow Max Mode Optimization Logic Drops More Max Mode Optimization Close To Tape Out: Min Mode Analysis and Fixes Challenges: Resizing bits in banks? Repeater reposition? Room for more repeaters? Don’t aggravate critical paths!

4. Outline • Motivation • Modelling late & early modes concurrently • Identifying sub-optimal solutions in a list • The merging problem • Power-Delay Trade-Off • Interaction between late & early modes (examples) • Conclusions, limitations, and future directions • Acknowledgements

5. Basic Algorithm in the Late Mode Try repeater sizes to generate solutions: (c, q) pairsIdentify and prune sub-optimal; Merging @ fanout: avoid sub-optimal combinationsSelect the solution with highest q @ driver

6. Concurrent Min-Max Model Solution: (cw, qw, cb, qb) Objective Function: Late-Mode qw Constraint: Early-Mode Arrival Time at the Driver: qbd s2 is sub-optimal compared to s1 if (s1 => s2) s2 is sub-optimal in late mode and s2 is sub-optimal in early mode Late mode: s1 => s2 if (cw2 < cw1) and (qw2 < qw1) qb close to qbd is better higher c helps to achieve qb closer to qbd (Note: initially qb  qbd) if (cb1 < cb2) and (qb1 qb2): (cb2, qb2) => (cb1, qb1)

7. Outline • Motivation • Modelling late & early modes concurrently • Identifying sub-optimal solutions in a list • The merging problem • Power-Delay Trade-Off • Interaction between late & early modes (examples) • Conclusions, limitations and future directions • Acknowledgements

8. Pruning a List of Solutions • Four rules: cw2  cw1 in all cases: • Case I: qb1 > qbd and qb2qbd: • Case II: qb1 > qbd and qb2 > qbd: • Case III: qb1 qbd and qb2qbd: • Case IV: qb1qbd and qb2 > qbd: s2 cannot be pruned Prune s1 if (cw1 = cw2) and (qw1qw2) • Prune s2 if (qw2qw1), (cb2cb1) and (qb2 qb1) • Prune s1 if (qw1qw2), (cw1 = cw2), (cb1cb2), (qb1 qb2) Prune s2 if (qw2qw1) Prune s1 if (cw1 = cw2), and (qw1qw2) Prune s2 if (qw2qw1)

9. Identifying sub-optimal solutions • Solution cw qw • 1 10 100 • 2 11 102 • 3 13 101 • 4 15 106 • 5 15 105 • 6 16 104 • 7 17 103 • 8 18 103 • 9 19 109 • 10 20 110 • 11 21 108 • 12 22 109 • 13 22 111 • 14 23 109 • 15 24 110 cb qb 5 50 6 51 6 52 7 52 8 54 9 55 6 55 8 54 10 56 11 57 12 58 13 59 14 60 9 57 11 56 Dominating Sol. 2 5 5 9

10. Complexity Reduction in Pruning

11. Further Reduction in Comparison Set Set G can be stored in a 2-Way binary tree: 1st branch: qw 2nd branch: qb How to quickly identify the dominating solution 9 in group G?

12. qw {1,2,6,5,4,11} {9,12,10,13} qb {9} {12,10,13} Example Binary Tree Solution 14: cw=23 qw=109 cb=9 qb=57 Dominating Solution: 9: cw=19 qw=109 cb=10 qb=56 G = {1,2,6,5,4,11,9,12,10,13}

13. Outline • Motivation • Modelling late & early modes concurrently • Identifying sub-optimal solutions in a list • The merging problem • Power-Delay Trade-Off • Interaction between late & early modes (examples) • Conclusions, limitations and future directions • Acknowledgements

14. Merging Multiple Branches

15. Late Mode Merging LS = {(1,1)->(1X{2:3}), (2,2)->(2,3)}

16. Early Mode Merging ES = {(2,2)->(2X{1,3}), (1,2)->(1X{1,3})}

17. Identifying Non-Suboptimal Combinations LS = {(1,1)->(1X{2:3}), (2,2)->(2,3)} ES = {(2,2)->(2X{1,3}), (1,2)->(1X{1,3})} Sub-Optimal combinations are: (2,3) Non-suboptimal combinations: (1,2), (1,3), (2,1), and (1,1) __________ _____ Looking for a more efficient technique

18. Outline • Motivation • Modelling late & early modes concurrently • Identifying sub-optimal solutions in a list • The merging problem • Power-Delay Trade-Off • Interaction between late & early modes (examples) • Conclusions, limitations and future directions • Acknowledgements

19. Delay-Power Trade-Off How to avoid the flat region?

20. Techniques for Trade-Off John Lillis (ICCAD-95) • Prune a solution if inferior in both p and q • Algorithm highlights: Put solutions into power bins Intra-bin Pruning: Linear Inter-bin Pruning: more than linear Merging: all bin-pairs All trade-offs are explicitly computed and retained Final selections at the driver • Issues: Large # of bins (esp. if slew dependent) Number of bin-pairs can be O(n2) Large solution space => run time

21. Implicit Power-Delay Trade-Off Desired trade-off is captured in a parameter: l = Ddelay/Dpower For example, if 0.01 ps delay reduction for a power dissipation of 1 mw is acceptable, then l = 0.01 ps/mw qa = q - l*P (P = power/area); l*P is a “penalty” Features: Trade-Off is Implicit Controlled Solution Space and Run Time Pruning a list: if (c2 c1) and (q2a < q1a) (c1, q1a) => (c2, q2a): Facilitates min-power solution (test nets) Merging Much detailed: could not include in this paper

22. Too Little to Gain @ Too Much Price Penalty #net buffered #repeaters0.0 2304 51260.5 1928 2628

23. Outline • Motivation • Modelling late & early modes concurrently • Identifying sub-optimal solutions in a list • The merging problem • Power-Delay Trade-Off • Interaction between late & early modes (examples) • Conclusions, limitations and future directions • Acknowledgements

24. Interaction Betwn. Late & Early Modes

25. Conclusion & Future Directions A new model for repeater insertion problem Early-mode timing requirement is a constraint Helps avoid aggressive late-mode optimization creating new early mode violations Should speed up design turn-around time by avoiding ECO’s to satisfy early-mode violations Techniques for satisfying maximum and minimum slew values, accurate timing to consider these slew values and avoid the flat region in the power-delay curve

26. Limitations & Future Directions Limitations Run time complexity Slack Budgeting Future research topics include: Combine gate sizing and repeater insertion Cone based Graph based Better merging techniques Controlling variations: process, voltage and temperature Hierarchical We welcome collaboration with academia

27. Acknowledgements • Reviewers for detailed feedback • Rob Mains for review & encouragements • Aman Joshi and Sun Management for support • Program Committee and the Organizers

28. Thank You

29. Satisfying Min-Max Slews