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Elementary Microarchitecture Algebra

Elementary Microarchitecture Algebra. John Matthews and John Launchbury Oregon Graduate Institute. Hawk Goals. Develop specifications that are clear and concise Simulate the specifications, both concretely and symbolically Formally verify specifications at the source-code level.

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Elementary Microarchitecture Algebra

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  1. Elementary Microarchitecture Algebra John Matthews and John Launchbury Oregon Graduate Institute

  2. Hawk Goals • Develop specifications that are clear and concise • Simulate the specifications, both concretely and symbolically • Formally verify specifications at the source-code level

  3. Algebraic Verification • Developed a domain-specific algebra for microarchitectures • Proved equational laws that hold between microarchitecture components • We simplify pipelines using these laws while preserving functional (cycle-accurate) behavior • But clock cycle period may change!

  4. Transactions • Group data and control information together • Transactions - containing destinations, sources, and operations - flow through the model • Decide control locally whenever possible R3 <- Add R1 R2 16 5 11

  5. Example: The SuperSimple Pipeline Reg ALU Reference machine: • Each transaction is completed in one (long) clock cycle • Results are written back to register file on the next clock cycle

  6. Example: The SuperSimple Pipeline Reg ALU Reference machine: R3 <- Add R1 R2 - - -

  7. Example: The SuperSimple Pipeline Reg ALU Reference machine: R3 <- Add R1 R2 R3 <- Add R1 R2 - - - - 5 11

  8. Example: The SuperSimple Pipeline Reg ALU Reference machine: R3 <- Add R1 R2 R3 <- Add R1 R2 R3 <- Add R1 R2 - - - - 5 11 16 5 11

  9. Example: The SuperSimple Pipeline Reg ALU Reference machine: R3 <- Add R1 R2 R3 <- Add R1 R2 R3 <- Add R1 R2 - - - - 5 11 16 5 11 R3 <- Add R1 R2 16 5 11

  10. Example: The SuperSimple Pipeline Reg ALU Reference machine: Reg ALU Pipelined machine:

  11. Verifying SuperSimple • Pipelined machine should behave the same as reference machine, except the pipelined machine has one more cycle of latency Reg ALU Reg ALU

  12. Verifying SuperSimple • We incrementally simplify the pipeline • Use local algebraic laws, each proved by induction over time Reg ALU Reg ALU

  13. Circuit Duplication Law • We can always duplicate a circuit without changing its functional behavior F F F

  14. Retiming the Pipeline • We first move delay circuits forward, using the circuit duplication law Reg ALU Reg ALU

  15. Retiming the Pipeline • We first move delay circuits forward, using the circuit duplication law Reg ALU Reg ALU

  16. Retiming the Pipeline • We first move delay circuits forward, using the circuit duplication law Reg ALU Reg ALU

  17. Time-Invariance Laws • Delay circuits can be moved across time-invariant circuits without changing behavior ALU ALU

  18. Retiming the Pipeline • Apply time-invariance laws to continue moving delay circuits Reg ALU Reg ALU

  19. Retiming the Pipeline • Apply time-invariance laws to continue moving delay circuits Reg ALU Reg ALU

  20. Retiming the Pipeline • Apply time-invariance laws to continue moving delay circuits Reg ALU Reg ALU

  21. Removing Forwarding Logic • The register-bypass laws allow us to remove a bypass circuit on the output of a registerFile Reg Reg Reg Reg

  22. Removing Forwarding Logic • Apply register-bypass law to remove bypass circuit Reg ALU Reg ALU

  23. Removing Forwarding Logic • Apply register-bypass law to remove bypass circuit Reg ALU Reg ALU

  24. Removing Forwarding Logic • Repositioning components Reg ALU Reg ALU

  25. Removing Forwarding Logic • Repositioning components Reg ALU Reg ALU

  26. Removing Forwarding Logic • Repositioning components Reg ALU Reg ALU

  27. Removing Forwarding Logic • Repositioning components Reg ALU Reg ALU

  28. Removing Forwarding Logic • Repositioning components Reg ALU Reg ALU

  29. Removing Forwarding Logic • Repositioning components Reg ALU Reg ALU

  30. Removing Forwarding Logic • Repositioning components Reg ALU Reg ALU

  31. Simplification Complete! • Pipeline has been reduced to reference machine, but delayed by one clock cycle Reg ALU Reg ALU

  32. Simplifying Stalling Pipelines • More complex pipelines often have to stall to resolve hazards or mis-speculation • A stalling pipeline won’t be cycle-accurate with respect to a reference machine • We still simplify as much as possible • Then use other verification techniques on simplified pipeline • Simplified pipeline should be easier to verify

  33. The SomewhatSimple Pipeline • Resolves mem-alu data hazards by stalling • Resolves branch mispredictions by squashing misp ? hazard? ICache Reg ALU Mem Kill

  34. misp ? hazard? ICache Reg ALU Mem Kill Original Pipeline

  35. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  36. misp ? hazard? ICache Reg ALU Mem Kill Various Retiming Laws Simplifying pipeline .....

  37. misp ? hazard? ICache Reg ALU Mem Kill Various Retiming Laws Simplifying pipeline .....

  38. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  39. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  40. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  41. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  42. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  43. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  44. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  45. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  46. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  47. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  48. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  49. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

  50. misp ? hazard? ICache Reg ALU Mem Kill Simplifying pipeline .....

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