Accupower an accurate power estimation tool for superscalar microprocessors
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AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors*. Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose Department of Computer Science State University of New York Binghamton, NY 13902-6000 http://www.cs.binghamton.edu/~lowpower.

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AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors*

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Accupower an accurate power estimation tool for superscalar microprocessors

DATE’02

AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors*

Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose

Department of Computer Science

State University of New York

Binghamton, NY 13902-6000

http://www.cs.binghamton.edu/~lowpower

5th Design, Automation and Test in Europe Conference (DATE-02), March 2002

*supported in part by DARPA through the PAC-C program and NSF


Motivation

DATE’02

Motivation

  • Power dissipation is an increasingly important issue for both embedded systems and high-end superscalar CPUs

  • Accurate power estimation tools are needed

  • Existing publicly available tools:

    • Wattch, TEM2P2EST (both based on Simplescalar)

    • SimplePower (not applicable to superscalar datapaths)


Motivation cont

DATE’02

Motivation (cont)

  • Simplescalar: lumps the issue queue, the reorder buffer (ROB) and the physical register file (PRF) into the Register Update Unit (RUU).

  • Real datapaths:

    • issue queues, ROBs and PRFs are implemented as separate structures

    • Number of entries and number of ports to these structures are quite disparate.

  • Thus: power can not be estimated accurately using Simplescalar


Accupower 3 components

DATE’02

AccuPower: 3 components

  • True cycle-level microarchitectural simulators for three datapath variations currently in use

  • Library of VLSI layouts for major datapath components

  • Power estimator


Power estimation methodology

DATE’02

Power Estimation Methodology

Compiled

SPEC benchmarks

Performance stats

Microarchitectural

Simulator

Two separate threads

Datapath

specs

Transition counts,

Context information

Inter-thread

buffers

Data analyzer/

Intra-stream analysis

Energy/Power

Estimator

VLSI layout

data

Power/energy

stats

SPICE

SPICE

decks

SPICE measures of

Energy per transition


Datapath a

DATE’02

Datapath A

Physical Register

File

Instruction Issue

Architectural register file

PRF

Function Units

FU1

D/RN

Fetch

RF /Dis

FU2

ROB

ARF

IQ

FUm

Instruction dispatch

EX

Result forwarding buses


Datapath b

DATE’02

Datapath B

Physical Register

File

Instruction Issue

Architectural register file

PRF

Function Units

ROB

FU1

D/RN

Fetch

RF /Dis

FU2

ARF

IQ

FUm

Instruction dispatch

EX

Status update


Datapath c

DATE’02

Datapath C

Instruction Issue

Architectural register file

Function

Units

FU1

Fetch

D/RN/Dispatch

FU2

ROB / PRF

ARF

IQ

FUm

Instruction dispatch

EX

Result/status forwarding buses


Accupower features

DATE’02

AccuPower features

  • Detailed cycle-level simulation of major datapath components and interconnections

  • Detailed and accurate simulation of the on-chip cache hierarchy

  • Built-in models of three major datapath variations

  • Implementation of cutting-edge techniques for power/energy reduction at the microarchitectural and circuit-level

  • Use of SPICE coefficients for accuracy


Microarchitectural simulators

DATE’02

Microarchitectural simulators

  • Actual out-of-order execution is modeled

  • 2-cycle pipelined fetch mechanism is implemented

  • Contention for the bus between L1 and L2 caches is modeled, as well as the contention for the off-chip interconnection

  • Decode/Rename/Dispatch mechanism is implemented as 2 pipeline stages.

  • Realistic forwarding delays are assumed


Using accupower

DATE’02

Using AccuPower

  • Raw data collection

    • Bit-level datapath activity on the interconnection, transfer links

    • Read/write activity of the register files implementing major storage components

  • Monitoring of individual resource occupancies

  • Accurate component-level power estimation

  • Exploration of various power reduction techniques

  • Exploration of alternative architectures


Resource usage in superscalar datapath example fpppp

DATE’02

Resource Usage in Superscalar Datapath: Example (fpppp)


Experimental results from accupower

DATE’02

Experimental Results from AccuPower

%

% of bits not driven using bit-slice invariance on top of

Zero-byte encoding for Datapath A


Experimental results from accupower1

DATE’02

Experimental Results from AccuPower

%

% of bits not driven using bit-slice invariance on top of

Zero-byte encoding for Datapath B


Experimental results from accupower2

DATE’02

Experimental Results from AccuPower

Power (mW)

Power dissipation within the ROB for a 4-way superscalar processor (Datapath C)


Experimental results from accupower3

DATE’02

Experimental Results from AccuPower

Power (mW)

Power dissipation in the issue queue


Concluding remarks

DATE’02

Concluding remarks

  • AccuPower is a collection of microarchitectural simulators, library of VLSI layouts and the power estimator

  • The tool provides capabilities for ACCURATE analysis of power/performance tradeoffs in a superscalar processor.

  • Public release is planned in the near future.


Accupower an accurate power estimation tool for superscalar microprocessors1

DATE’02

AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors*

Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose

Department of Computer Science

State University of New York

Binghamton, NY 13902-6000

e-mail: [email protected]

http://www.cs.binghamton.edu/~lowpower

5th Design, Automation and Test in Europe Conference (DATE-02), March 2002

*supported in part by DARPA through the PAC-C program and NSF


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