Digital integrated circuits a design perspective
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Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikoli ć. Designing Combinational Logic Circuits. November 2002. Combinational vs. Sequential Logic. Combinational. Sequential. Output =. (. ). f. In, Previous In. Output =. (. ). f. In.

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Digital integrated circuits a design perspective

Digital Integrated CircuitsA Design Perspective

Jan M. Rabaey

Anantha Chandrakasan

Borivoje Nikolić

Designing CombinationalLogic Circuits

November 2002.


Combinational vs sequential logic

Combinational vs. Sequential Logic

Combinational

Sequential

Output =

(

)

f

In, Previous In

Output =

(

)

f

In


Static cmos circuit

At every point in time (except during the switching

transients) each gate output is connected to either

V

or

V

via a low-resistive path.

DD

ss

The outputs of the gates assumeat all timesthevalue

of the Boolean function, implemented by the circuit

(ignoring, once again, the transient effects during

switching periods).

This is in contrast to the

dynamic

circuit class, which

relies on temporary storage of signal values on the

capacitance of high impedance circuit nodes.

Static CMOS Circuit


Static complementary cmos

Static Complementary CMOS

VDD

In1

PMOS only

In2

PUN

InN

F(In1,In2,…InN)

In1

In2

PDN

NMOS only

InN

PUN and PDN are dual logic networks


Nmos transistors in series parallel connection

NMOS Transistors in Series/Parallel Connection

  • Transistors can be thought as a switch controlled by its gate signal

  • NMOS switch closes when switch control input is high


Pmos transistors in series parallel connection

PMOS Transistors in Series/Parallel Connection


Threshold drops

CL

CL

CL

CL

Threshold Drops

VDD

VDD

PUN

S

D

VDD

D

S

0  VDD

0  VDD - VTn

VGS

PDN

VDD 0

VDD |VTp|

VGS

D

S

VDD

S

D


Complementary cmos logic style

Complementary CMOS Logic Style


Example gate nand

Example Gate: NAND


Example gate nor

Example Gate: NOR


Complex cmos gate

B

A

C

D

Complex CMOS Gate

OUT = D + A • (B + C)

A

D

B

C


Constructing a complex gate

Constructing a Complex Gate


Properties of complementary cmos gates snapshot

Properties of Complementary CMOS Gates Snapshot

High noise margins

:

V

and

V

are at

V

and

GND

, respectively.

OH

OL

DD

No static power consumption

:

There never exists a direct path between

V

and

DD

V

(

GND

) in steady-state mode

.

SS

Comparable rise and fall times:

(under appropriate sizing conditions)


Cmos properties

CMOS Properties

  • Full rail-to-rail swing; high noise margins

  • Logic levels not dependent upon the relative device sizes; ratioless

  • Always a path to Vdd or Gnd in steady state; low output impedance

  • Extremely high input resistance; nearly zero steady-state input current

  • No direct path steady state between power and ground; no static power dissipation

  • Propagation delay function of load capacitance and resistance of transistors


Switch delay model

Rp

Rp

Rp

Rp

Rp

Rp

A

A

A

B

B

A

Cint

Rn

CL

CL

CL

Rn

Rn

Rn

Rn

B

A

B

A

A

Cint

Switch Delay Model

Req

A

A

NOR2

INV

NAND2


Input pattern effects on delay

Rp

Rp

B

A

Cint

CL

Rn

A

Input Pattern Effects on Delay

  • Delay is dependent on the pattern of inputs

  • Low to high transition

    • both inputs go low

      • delay is 0.69 Rp/2 CL

    • one input goes low

      • delay is 0.69 Rp CL

  • High to low transition

    • both inputs go high

      • delay is 0.69 2Rn CL

Rn

B


Delay dependence on input patterns

Delay Dependence on Input Patterns

A=B=10

A=1 0, B=1

A=1, B=10

Voltage [V]

time [ps]

NMOS = 0.5m/0.25 m

PMOS = 0.75m/0.25 m

CL = 100 fF


Transistor sizing

Rp

Rp

2

2

Rp

Rp

B

A

B

A

Rn

Cint

Cint

CL

CL

Rn

Rn

Rn

B

A

B

A

1

1

Transistor Sizing

4

4

2

2


Transistor sizing a complex cmos gate

A

D

Transistor Sizing a Complex CMOS Gate

B

8

6

4

3

C

8

6

4

6

OUT = D + A • (B + C)

A

2

D

1

B

2

C

2


Fan in considerations

D

C

B

A

C3

C2

C1

CL

Fan-In Considerations

A

Distributed RC model

(Elmore delay)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

B

C

D


T p as a function of fan in

quadratic

tpHL

tp

linear

tp as a Function of Fan-In

Gates with a fan-in greater than 4 should be avoided.

tp (psec)

tpLH

fan-in


T p as a function of fan out

tp as a Function of Fan-Out

All gates have the same drive current.

tpNOR2

tpNAND2

tpINV

tp (psec)

Slope is a function of “driving strength”

eff. fan-out


T p as a function of fan in and fan out

tp as a Function of Fan-In and Fan-Out

  • Fan-in: quadratic due to increasing resistance and capacitance

  • Fan-out: each additional fan-out gate adds two gate capacitances to CL

    tp = a1FI + a2FI2 + a3FO


Fast complex gates design technique 1

C3

C2

C1

CL

Fast Complex Gates:Design Technique 1

  • Transistor sizing

    • as long as fan-out capacitance dominates

  • Progressive sizing

Distributed RC line

M1 > M2 > M3 > … > MN

(the fet closest to the

output is the smallest)

InN

MN

In3

M3

In2

M2

Can reduce delay by more than 20%; decreasing gains as technology shrinks

In1

M1


Fast complex gates design technique 2

C2

C1

C1

C2

CL

CL

Fast Complex Gates:Design Technique 2

  • Transistor ordering

critical path

critical path

01

charged

charged

1

In1

In3

M3

M3

1

1

In2

In2

M2

discharged

M2

charged

1

In3

discharged

In1

charged

M1

M1

01

delay determined by time to discharge CL, C1 and C2

delay determined by time to discharge CL


Fast complex gates design technique 3

Fast Complex Gates:Design Technique 3

  • Alternative logic structures

F = ABCDEFGH


Fast complex gates design technique 4

CL

CL

Fast Complex Gates:Design Technique 4

  • Isolating fan-in from fan-out using buffer insertion


Fast complex gates design technique 5

Fast Complex Gates:Design Technique 5

  • Reducing the voltage swing

    • linear reduction in delay

    • also reduces power consumption

  • But the following gate is much slower!

  • Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design)

tpHL= 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )


Sizing logic paths for speed

Sizing Logic Paths for Speed

  • Frequently, input capacitance of a logic path is constrained

  • Logic also has to drive some capacitance

  • Example: ALU load in an Intel’s microprocessor is 0.5pF

  • How do we size the ALU datapath to achieve maximum speed?

  • We have already solved this for the inverter chain – can we generalize it for any type of logic?


Buffer example

Buffer Example

In

Out

CL

1

2

N

(in units of tinv)

For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4

How to generalize this to any logic path?


Ratioed logic

Ratioed Logic


Ratioed logic1

Ratioed Logic


Ratioed logic2

Ratioed Logic


Active loads

Active Loads


Pseudo nmos

Pseudo-NMOS


Pseudo nmos vtc

Pseudo-NMOS VTC

3.0

2.5

W/L

= 4

2.0

p

1.5

[V]

W/L

= 2

t

u

p

o

V

1.0

W/L

= 0.5

W/L

= 1

p

p

0.5

W/L

= 0.25

p

0.0

0.0

0.5

1.0

1.5

2.0

2.5

V

[V]

in


Improved loads 2

Improved Loads (2)

V

V

DD

DD

M1

M2

Out

Out

A

A

PDN1

PDN2

B

B

V

V

SS

SS

Differential Cascode Voltage Switch Logic (DCVSL)


Dcvsl example

DCVSL Example


Dcvsl transient response

2.5

1.5

0.5

-0.5

0

0.2

0.4

0.6

0.8

1.0

DCVSL Transient Response

A B

[V]

e

A B

g

a

t

l

o

A

,

B

V

A,B

Time [ns]


Pass transistor logic

Pass-TransistorLogic


Pass transistor logic1

Pass-Transistor Logic


Example and gate

Example: AND Gate


Nmos only logic

NMOS-Only Logic

3.0

In

Out

2.0

[V]

x

e

g

a

t

l

o

V

1.0

0.0

0

0.5

1

1.5

2

Time [ns]


Nmos only switch

NMOS-only Switch

V

C =

2.5 V

C =

2.5

M

2

A =

2.5 V

B

A =

2.5 V

M

n

B

M

C

1

L

V

does not pull up to 2.5V, but 2.5V -

V

TN

B

Threshold voltage loss causes

static power consumption

NMOS has higher threshold than PMOS (body effect)


Nmos only logic level restoring transistor

NMOS Only Logic: Level Restoring Transistor

V

DD

V

DD

Level Restorer

M

r

B

M

2

X

M

A

Out

n

M

1

• Advantage: Full Swing

• Restorer adds capacitance, takes away pull down current at X

• Ratio problem


Restorer sizing

2.0

1.0

0.0

0

100

200

300

400

500

Restorer Sizing

3.0

  • Upper limit on restorer size

  • Pass-transistor pull-downcan have several transistors in stack

W

/

L

=1.75/0.25

[V]

r

e

W

/

L

=1.50/0.25

g

r

a

t

l

o

V

W

/

L

=1.25/0.25

W

/

L

=1.0/0.25

r

r

Time [ps]


Solution 2 single transistor pass gate with v t 0

Solution 2: Single Transistor Pass Gate with VT=0

V

DD

V

DD

0V

2.5V

Out

0V

V

DD

2.5V

WATCH OUT FOR LEAKAGE CURRENTS


Complementary pass transistor logic

Complementary Pass Transistor Logic


Solution 3 transmission gate

Solution 3: Transmission Gate

C

C

A

A

B

B

C

C

C =

2.5 V

A =

2.5 V

B

C

L

C

= 0 V


Resistance of transmission gate

Resistance of Transmission Gate


Pass transistor based multiplexer

S

S

Pass-Transistor Based Multiplexer

S

VDD

GND

In1

In2

S


Transmission gate xor

Transmission Gate XOR

B

B

M2

A

A

F

M1

M3/M4

B

B


Delay in transmission gate networks

2.5

2.5

2.5

2.5

V

V

V

V

V

V

1

i

n-1

i-1

i+1

n

In

C

C

C

C

C

0

0

0

0

(a)

R

R

R

R

eq

eq

eq

eq

V

V

V

V

V

1

n-1

i

i+1

n

In

C

C

C

C

C

(b)

R

R

R

eq

eq

eq

C

C

C

C

Delay in Transmission Gate Networks

m

R

R

R

eq

eq

eq

In

C

C

C

C

(c)


Delay optimization

Delay Optimization


Transmission gate full adder

Transmission Gate Full Adder

Similar delays for sum and carry


Dynamic logic

Dynamic Logic


Dynamic cmos

Dynamic CMOS

  • In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.

    • fan-in of n requires 2n (n N-type + n P-type) devices

  • Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.

    • requires on n + 2 (n+1 N-type + 1 P-type) transistors


Dynamic gate

Clk

Mp

((AB)+C)

Out

CL

A

C

B

Clk

Me

Dynamic Gate

off

Clk

Mp

on

1

Out

In1

In2

PDN

In3

Clk

Me

off

on

Two phase operation

Precharge (Clk = 0)

Evaluate (Clk = 1)


Conditions on output

Conditions on Output

  • Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.

  • Inputs to the gate can make at most one transition during evaluation.

  • Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL


Properties of dynamic gates

Properties of Dynamic Gates

  • Logic function is implemented by the PDN only

    • number of transistors is N + 2 (versus 2N for static complementary CMOS)

  • Full swing outputs (VOL = GND and VOH = VDD)

  • Non-ratioed - sizing of the devices does not affect the logic levels

  • Faster switching speeds

    • reduced load capacitance due to lower input capacitance (Cin)

    • reduced load capacitance due to smaller output loading (Cout)

    • no Isc, so all the current provided by PDN goes into discharging CL


Properties of dynamic gates1

Properties of Dynamic Gates

  • Overall power dissipation usually higher than static CMOS

    • no static current path ever exists between VDD and GND (including Psc)

    • no glitching

    • higher transition probabilities

    • extra load on Clk

  • PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn

    • low noise margin (NML)

  • Needs a precharge/evaluate clock


Issues in dynamic design 1 charge leakage

CL

Issues in Dynamic Design 1: Charge Leakage

CLK

Clk

Mp

Out

A

Evaluate

VOut

Clk

Me

Precharge

Leakage sources

Dominant component is subthreshold current


Solution to charge leakage

CL

Solution to Charge Leakage

Keeper

Clk

Mp

Mkp

A

Out

B

Clk

Me

Same approach as level restorer for pass-transistor logic


Issues in dynamic design 2 charge sharing

CL

CA

CB

Issues in Dynamic Design 2: Charge Sharing

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

Clk

Mp

Out

A

B=0

Clk

Me


Charge sharing example

Cd=10fF

CL=50fF

Cb=15fF

Cc=15fF

Ca=15fF

Charge Sharing Example

Clk

Out

A

A

B

B

B

!B

C

C

Clk


Charge sharing

Charge Sharing

V

DD

M

Clk

p

Out

C

L

M

A

a

X

C

a

M

=

B

0

b

C

b

M

Clk

e


Solution to charge redistribution

Solution to Charge Redistribution

Clk

Clk

Mp

Mkp

Out

A

B

Clk

Me

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)


Issues in dynamic design 3 backgate coupling

CL1

CL2

Issues in Dynamic Design 3: Backgate Coupling

Clk

Mp

Out1

=1

Out2

=0

In

A=0

B=0

Clk

Me

Dynamic NAND

Static NAND


Backgate coupling effect

Backgate Coupling Effect

Out1

Voltage

Clk

Out2

In

Time, ns


Issues in dynamic design 4 clock feedthrough

CL

Issues in Dynamic Design 4: Clock Feedthrough

Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

Clk

Mp

Out

A

B

Clk

Me


Clock feedthrough

Clock Feedthrough

Clock feedthrough

Clk

Out

In1

In2

In3

In &

Clk

Voltage

In4

Out

Clk

Time, ns

Clock feedthrough


Other effects

Other Effects

  • Capacitive coupling

  • Substrate coupling

  • Minority charge injection

  • Supply noise (ground bounce)


Cascading dynamic gates

Clk

In

VTn

Out1

V

Out2

Cascading Dynamic Gates

V

Clk

Clk

Mp

Mp

Out2

Out1

In

Clk

Clk

Me

Me

t

Only 0  1 transitions allowed at inputs!


Domino logic

Domino Logic

Clk

Mp

Mkp

Clk

Mp

Out1

Out2

1  1

1  0

0  0

0  1

In1

In4

PDN

In2

PDN

In5

In3

Clk

Me

Clk

Me


Why domino

Ini

Ini

Ini

Ini

PDN

PDN

PDN

PDN

Inj

Inj

Inj

Inj

Why Domino?

Clk

Clk

Like falling dominos!


Properties of domino logic

Properties of Domino Logic

  • Only non-inverting logic can be implemented

  • Very high speed

    • static inverter can be skewed, only L-H transition

    • Input capacitance reduced – smaller logical effort


Np cmos

np-CMOS

Clk

Me

Clk

Mp

Out1

1  1

1  0

In4

PUN

In1

In5

In2

PDN

0  0

0  1

In3

Out2

(to PDN)

Clk

Mp

Clk

Me

Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN


Nora logic

NORA Logic

Clk

Me

Clk

Mp

Out1

1  1

1  0

In4

PUN

In1

In5

In2

PDN

0  0

0  1

In3

Out2

(to PDN)

Clk

Mp

Clk

Me

to other

PDN’s

to other

PUN’s

WARNING: Very sensitive to noise!


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