Virtual memory
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Virtual Memory. Adapted from lecture notes of Dr. Patterson and Dr. Kubiatowicz of UC Berkeley. {. Thus far. {. Next: Virtual Memory. View of Memory Hierarchies. Regs. Upper Level. Instr. Operands. Faster. Cache. Blocks. L2 Cache. Blocks. Memory. Pages. Disk. Files. Larger.

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Virtual Memory

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Virtual memory

Virtual Memory

Adapted from lecture notes of Dr. Patterson and Dr. Kubiatowicz of UC Berkeley


View of memory hierarchies

{

Thus far

{

Next:

Virtual

Memory

View of Memory Hierarchies

Regs

Upper Level

Instr. Operands

Faster

Cache

Blocks

L2 Cache

Blocks

Memory

Pages

Disk

Files

Larger

Tape

Lower Level


Memory hierarchy some facts

Memory Hierarchy: Some Facts

Upper Level

Capacity

Access Time

Cost

Staging

Xfer Unit

faster

CPU Registers

100s Bytes

<10s ns

Registers

prog./compiler

1-8 bytes

Instr. Operands

Cache

K Bytes

10-100 ns

$.01-.001/bit

Cache

cache cntl

8-128 bytes

Blocks

Main Memory

M Bytes

100ns-1us

$.01-.001

Memory

OS

512-4K bytes

Pages

Disk

G Bytes

ms

10 - 10 cents

Disk

-4

-3

user/operator

Mbytes

Files

Larger

Tape

infinite

sec-min

10

Tape

Lower Level

-6


Virtual memory motivation

Virtual Memory: Motivation

  • If Principle of Locality allows caches to offer (usually) speed of cache memory with size of DRAM memory,then recursively why not use at next level to give speed of DRAM memory, size of Disk memory?

  • Treat Memory as “cache” for Disk !!!


Virtual memory

  • Share memory between multiple processes but still provide protection – don’t let one program read/write memory of another

  • Address space – give each program the illusion that it has its own private memory

    • Suppose code starts at addr 0x40000000. But different processes have different code, both at the same address! So each program has a different view of memory


Advantages of virtual memory

  • Translation:

    • Program can be given consistent view of memory, even though physical memory is scrambled

    • Makes multithreading reasonable (now used a lot!)

    • Only the most important part of program (“Working Set”) must be in physical memory.

    • Contiguous structures (like stacks) use only as much physical memory as necessary yet still grow later.

  • Protection:

    • Different threads (or processes) protected from each other.

    • Different pages can be given special behavior

      • (Read Only, Invisible to user programs, etc).

    • Kernel data protected from User programs

    • Very important for protection from malicious programs=> Far more “viruses” under Microsoft Windows

  • Sharing:

    • Can map same physical page to multiple users(“Shared memory”)

Advantages of Virtual Memory


Virtual to physical address translation

Virtual to Physical Address Translation

Program

operates in

its virtual

address

space

Physical

memory

(incl. caches)

HW

mapping

virtual

address

(inst. fetch

load, store)

physical

address

(inst. fetch

load, store)

  • Each program operates in its own virtual address space; ~only program running

  • Each is protected from the other

  • OS can decide where each goes in memory

  • Hardware (HW) provides virtual -> physical mapping


Mapping virtual memory to physical memory

Code

Static

Heap

Mapping Virtual Memory to Physical Memory

  • Divide into equal sizedchunks (about 4KB)

¥

Stack

  • Any chunk of Virtual Memory assigned to any chuck of Physical Memory (“page”)

Physical Memory

64 MB

0

0


Paging organization eg 1kb page

Virtual

Address

Physical

Address

page 0

0

1K

page 0

1K

0

page 1

1K

1024

1K

page 1

Addr

Trans

MAP

1024

...

...

...

page 2

1K

2048

...

...

...

page 7

1K

7168

page 31

1K

Physical

Memory

31744

Virtual Memory

Paging Organization (eg: 1KB Page)

Page is unit of mapping

Page also unit of transfer from disk to physical memory


Virtual memory mapping

Virtual Address:

page no.

offset

Page Table

...

Page Table

Base Reg

V

A.R.

P. P. A.

+

index

into

page

table

Access

Rights

Physical

Page

Address

Val

-id

Physical

Memory

Address

.

...

Virtual Memory Mapping

(actually,

concatenation)

Page Table located in physical memory


Issues in vm design

Issues in VM Design

What is the size of information blocks that are transferred from secondary to main storage (M)?  page size(Contrast with physical block size on disk, I.e. sector size)

Which region of M is to hold the new block placement policy

How do we find a page when we look for it?  block identification

Block of information brought into M, and M is full, then some region of M must be released to make room for the new block  replacement policy

What do we do on a write?  write policy

Missing item fetched from secondary memory only on the occurrence of a fault demand load policy

disk

mem

cache

reg

pages

frame


Virtual memory problem 1

Virtual Memory Problem # 1

  • Map every address  1 extra memory accesses for every memory access

  • Observation: since locality in pages of data, must be locality in virtual addresses of those pages

  • Why not use a cache of virtual to physical address translations to make translation fast? (small is fast)

  • For historical reasons, cache is called a Translation Lookaside Buffer, or TLB


Memory organization with tlb

Memory Organization with TLB

  • TLBs usually small, typically 128 - 256 entries

  • Like any other cache, the TLB can be fully associative, set associative, or direct mapped

hit

PA

miss

VA

TLB

Lookup

Cache

Main

Memory

Processor

miss

hit

Trans-

lation

data


Typical tlb format

Typical TLB Format

VirtualPhysicalDirtyRef Valid Access

Address AddressRights

  • TLB just a cache on the page table mappings

  • TLB access time comparable to cache (much less than main memory access time)

  • Ref: Used to help calculate LRU on replacement

  • Dirty: since use write back, need to know whether or not to write page to disk when replaced


What if not in tlb

What if not in TLB

  • Option 1: Hardware checks page table and loads new Page Table Entry into TLB

  • Option 2: Hardware traps to OS, up to OS to decide what to do

  • MIPS follows Option 2: Hardware knows nothing about page table format


Tlb miss

TLB Miss

  • If the address is not in the TLB, MIPS traps to the operating system

  • The operating system knows which program caused the TLB fault, page fault, and knows what the virtual address desired was requested

valid virtual physical

1

2

9


Tlb miss if data is in memory

TLB Miss: If data is in Memory

  • We simply add the entry to the TLB, evicting an old entry from the TLB

valid virtual physical

1

7

32

1

2

9


What if data is on disk

What if data is on disk ?

  • We load the page off the disk into a free block of memory, using a DMA transfer

    • Meantime we switch to some other process waiting to be run

  • When the DMA is complete, we get an interrupt and update the process's page table

    • So when we switch back to the task, the desired data will be in memory


What if the memory is full

What if the memory is full ?

  • We load the page off the disk into a least recently used block of memory, using a DMA transfer

    • Meantime we switch to some other process waiting to be run

  • When the DMA is complete, we get an interrupt and update the process's page table

    • So when we switch back to the task, the desired data will be in memory


Virtual memory problem 2

Virtual Memory Problem # 2

  • Page Table too big!

    • 4GB Virtual Memory ÷ 4 KB page ~ 1 million Page Table Entries 4 MB just for Page Table for 1 process, 25 processes  100 MB for Page Tables!

  • Variety of solutions to tradeoff memory size of mapping function for slower when miss TLB

    • Make TLB large enough, highly associative so rarely miss on address translation


Two level page tables

Virtual Memory

2nd Level

Page Tables

¥

Super

Page

Table

Stack

Physical

Memory

64

MB

...

Code

Static

Heap

0

0

Two Level Page Tables


Summary

Summary

  • Apply Principle of Locality Recursively

  • Reduce Miss Penalty? add a (L2) cache

  • Manage memory to disk? Treat as cache

    • Included protection as bonus, now critical

    • Use Page Table of mappings vs. tag/data in cache

  • Virtual memory to Physical Memory Translation too slow?

    • Add a cache of Virtual to Physical Address Translations, called a TLB


Summary1

Summary

  • Virtual Memory allows protected sharing of memory between processes with less swapping to disk, less fragmentation than always swap or base/bound

  • Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well

  • TLB to reduce performance cost of VM

  • Need more compact representation to reduce memory size cost of simple 1-level page table (especially 32-  64-bit address)


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