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Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer

Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer. Harry Porter, Ph.D. Portland State University November 7, 2007. +V. Double Throw Relay. Double Throw Relay. +V. Four Pole, Double Throw Relay. Four Pole, Double Throw Relay. +V. Schematic Diagrams.

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Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer

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  1. Slides to Accompanya Video Tutorial onHarry Porter’s Relay Computer • Harry Porter, Ph.D. • Portland State University • November 7, 2007

  2. +V

  3. Double Throw Relay

  4. Double Throw Relay +V

  5. Four Pole, Double Throw Relay

  6. Four Pole, Double Throw Relay +V

  7. Schematic Diagrams Assume other terminal is connected to ground

  8. Schematic Diagrams +V Assume other terminal is connected to ground

  9. The “NOT” Circuit 1 in out out +V 0 in inout 0 1 1 0 Convention: “1” = +12V “0” = not connected

  10. The “NOT” Circuit 0 in out out +V 1 in inout 0 1 1 0 Convention: “1” = +12V “0” = not connected

  11. The “OR” Circuit b b or c c +V b c OUT 0 0 0 0 1 1 1 0 1 1 1 1 b b or c +V c

  12. An Optimization? b b b or c c b or c c

  13. An Optimization? b b b or c b or c c c or d c d c or d d

  14. An Optimization? b b b or c b or c c c or d c d c or d Whoops! d

  15. An Optimization? b b b or c b or c c +V c or d c or d c d d

  16. 1-Bit Logic Circuit b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 NOT b AND OR c XOR

  17. 1-Bit Logic Circuit b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 V NOT b AND OR c XOR

  18. 1-Bit Logic Circuit b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 V NOT b AND OR c XOR

  19. 1-Bit Logic Circuit b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 V NOT b AND OR c XOR

  20. 1-Bit Logic Circuit b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 V NOT b AND OR c XOR

  21. 1-Bit Logic Circuit b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 V NOT b AND OR c XOR

  22. Eight 1-bit circuits can be combinedto build an...8-Bit Logic Circuit B1 C1 B0 C0 B7 C7 Logic Circuit Logic Circuit Logic Circuit • • • XOR1 XOR0 XOR7 OR1 OR0 OR7 AND1 AND0 AND7 NOT1 NOT0 NOT7

  23. The “Full Adder” Circuit Cyin B C Cyout Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 B C Carryout Carryin Full Adder Sum

  24. 8 full-adders can be combined to build an...8-Bit Adder B7 C7 B1 C1 B0 C0 Carry Carry Carry Full Adder Full Adder Full Adder 0 • • • Sum7 Sum1 Sum0 8 B 8 Sum + Carry 8 C

  25. The Zero-Detect Circuit Zero V+ Result Bus

  26. The Zero-Detect Circuit Zero V+ Result Bus Sign

  27. Enable Circuit Enable

  28. B XOR C Enable Circuit x5 x7 x6 x4 x1 x3 x2 x0 Enable Result Bus

  29. B Shift Left Circular (SHL) b5 b7 b6 b4 b1 b3 b2 b0 Enable Result Bus

  30. 3-to-8 Decoder f0 f1 f2 OUTPUT 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 ADD INC AND OR XOR NOT V SHL f0 <unused> f1 f2

  31. Arithmetic Logic Unit (ALU) B 8 C 8 Function 3 8-bit Adder 8-bit Logic SHL INC ADD AND NOT XOR OR 3-to-8 Decoder Enable En En En En En En Data Bus 8 Zero-Detect Sign Zero Carry

  32. An 8-Bit ALU 3 Function Code 000 add 001 inc 010 and 011 or 100 xor 101 not 110 shl 111 <nop> 8 B 8 Result ALU 8 C Carry Sign Zero

  33. Register Storage +V A

  34. Register Storage • • • +V A7 A6 A0

  35. Register Storage • • • +V A7 A6 A0 Select Enable Bus

  36. Register Storage • • • A7 A6 A0 Load Select Enable Bus

  37. Register Storage • • • A7 A6 A0 Load Select Enable Bus

  38. 8-Bit Registers “Y” Register “X” Register Load Load Select Select 8-Bit “Data” Bus

  39. 16-Bit “Address” Bus Load Select “Y” Register “X” Register Load Load Select Select 8-Bit “Data” Bus

  40. 8-bit ALU 16-bit Increment Inc A B C D Z Cy S M1 M M2 X XY Y SystemArchitecture J1 J 8-bit Data Bus J2 Inst 16-bit Address Bus PC Memory Addr Data

  41. 32K Byte Static RAM Chip LEDs 8 FET Power Transistors (to drive relays during a memory-read operation)

  42. 8-bit ALU 16-bit Increment Inc A B C D Z Cy S M1 M M2 X XY Example:The ALU Instruction Y J1 J 8-bit Data Bus J2 16-bit Address Bus Inst PC Memory Addr Data

  43. 8-bit ALU 16-bit Increment Inc A B C D Z Cy S M1 M M2 X XY Step 1:Fetch Instruction Y J1 J 8-bit Data Bus J2 16-bit Address Bus Inst PC LOAD MEM-READ SELECT Memory Addr Data

  44. 8-bit ALU A B C D Z Cy S M1 M M2 X XY Step 2:Increment PC Y J1 J 8-bit Data Bus J2 16-bit Address Bus Inst PC Inc SELECT LOAD 16-bit Increment Memory Addr Data

  45. 8-bit ALU A B C D Z Cy S M1 M M2 X XY Y Step 3:Update PC J1 J 8-bit Data Bus J2 16-bit Address Bus Inst PC Inc LOAD SELECT 16-bit Increment Memory Addr Data

  46. 8-bit ALU A B LOAD C D Z Cy S M1 M LOAD M2 FUNCTION X XY Y J1 Step 4:Execute Instruction J 8-bit Data Bus J2 16-bit Address Bus Inst PC Inc 16-bit Increment Memory Addr Data

  47. Clock +V Output Switch +V

  48. Clock +V Output Switch +V Charging

  49. Clock +V Output Switch +V Discharging

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