Performed by: Yaron Recher & Shai Maylat Supervisor: Mr. Rolf Hilgendorf

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Sub -NyquistSampling System Architecture Characterization presentation Performed by: YaronRecher & ShaiMaylat Supervisor: Mr. Rolf Hilgendorf סמסטר אביב 2010

2. Project Overview • Design system architecture • Creating debug environment • Architecture implementation on FPGA • Creating controlling GUI

3. General Algorithm Scheme • Expand block: Recieves 4 channels from A/D and expandsthem to 12 channels (18bit each) • CTF block:Discovers supports out of 12 channels (support width 7 bit) • DSP & Detector block**: Reconstructs the Initial Signal ** Implemented in the same FPGA

4. FPGA Environment 1x BOARD: ProcStar||| GiDEL 4x FPGA: Stratix||| EP3SE110 Altera Overview

5. PROCStar III Processing unit

6. Buses on Board • FPGA to FPGA BitsMax.Freq.(MHz) • L/R (I/O) : 100 250 // exp. IC4 • V18_L/R : 10 300 • Main : 40 300 // global • FPGAto PSDBBits Max.Freq.(MHz) • L/R_IO : 20 300 // 7 to IC1 • L_IN : 8 300 // PSDB to IC • L2_IO : 85 300 // only to IC1

7. Memories • External from FPGA • Bank A: 256 MB DDR2 DRAM • Bank B,C: 2 x 1 GB SODIMM • Internal inside FPGA • MLAB 640-bit (639 blocks) • Filter delay lines, small FIFO buffers and shift registers • M9K Blocks 9,216-bit (16 blocks) • General purpose memory applications • M114K Blocks 147,456-bit (2150 blocks) • Processor code storage, packet and video frame buffering. Max.Freq.=333MHz B Max.Freq.= 333MHz C Max.Freq.=166MHz Max.Freq.=500MHz Total Internal Memory: 1MByte

8. Project Goals • Integrate Designs – Across linked FPGA’s • Set and support Test environment • Design and Implement Debug GUI • Improve Debug GUI to work environment GUI

9. General Connectivity 60MHz 20MHz \2MHz 20MHz 20MHz 20MHz

10. Process FlowSimilar to all Units Loading data on board FIFOs from PCI Loading control registers from PCI Transferring data to internal RAMs from external memory Sending Start Loading signal to CTF/DSP/Exp. Units Receiving Ready signal from the CTF/DSP/Exp. Units Sending Ready signal to the main controller. All units ready Main controller Starts the A2D and the system runs

11. Expander Entity Outputs: ready_to_arch – finished initilization data_to_main – main output to CTF/DSP (20[MHz]) data_to_main_valid – main output is valid data_to_CTF – iteration output (2[MHz]) data_to_CTF_valid – iteration output is valid memory_read_request – request data from memory Inputs: Clk_60 – 60MHz input data clock Clk_20 – 20MHz main output data clock Clk_2 – 2MHz iteration output data clock Clk_240 – 240MHz processing clock From main controller : rst – reset start_load – memory ready for read num_of_itr – number of wanted slice pause – pause the system From CTF : req_pulse – request of new slice Memory (20[MHz]) : memory_data – data from memory memory_ack – requested data is ready From A/D (60[MHz]) : Data_from_AD – input data for the system Data_in_valid – the input is valid

12. Designed till now: Blocks to implement: Expander BlocksIncluding on Board Memories Block Description • A2D : FIFO on board memory • Coeff. : FIFO on board memory • Main Bus Debug : FIFO on board memory • CTFDebug : FIFO on board memory • A2D Reader : Reads data from A2D, simulates A2D input • Main Debug Writer : Writes data from main bus to on board FIFO • CTF Debug Writer : Writes data from Expander to debug memory • Main Bus Interface : Receives data from Expander & sends with high rate • CTF Bus Interface : Receives data from Expander & sends with high rate • Main Controller : Controls the system operation • Registers : Contain control data received from PCI • Pll : On board Pll , similar to all

13. Designed till now: (not yet ON FPGA) Expander Block Diagram Blocks to implement:

14. Designed till now: Expander State Machine Path to implement:

15. CTF Entity Inputs: Clk_20 – 20MHz main input data clock Clk_240 – 240MHz processing clock CLk 160 - 160MHz processing clock or as needed From controller : reset – reset start_load– memory ready for read pause – pause the system N_Frame – Frame Threshhold - OMP stopping cond. Num_Of_Ite r- Number of iterations From Expander : data_from_exp – iterational data data_exp_valid - iterational data valid From DSP : initiate – there has been support change From Matrix RAM: A_data – data from RAM From Main interface: data_main– input data for the expander data_main_valid– the data is valid Outputs: To Controller : ready – ready to begin To Expander : req_pulse – requests next iteration To DSP : support – numbers of support num_of_supports – total number of supports support_valid – support data is valid To Matrix RAM : A_addr – Address for data from RAM A_rd_req – read enable

16. Designed till now: Blocks to implement: CTF BlocksIncluding on Board Memories Block Description • Iteration Debug : FIFO on board memory • Matrix : FIFO on board memory • Memory Debug : FIFO on board memory • Matrix internal : RAM memory • Main Reader : Reads data from memory, simulates input from Exp. main • Exp.DebugReader : Reads data from memory, simulates input from Exp. L/R • Matrix Writer : Reads ‘A’ matrix from memory, writes to internal memory • Memory Debug Writer: Writes Debug data to memory • Main Bus Interface : Receives data from main bus & sends with low rate • CTF Bus Interface : Receives data from L/R bus & sends with low rate • Exp. DebugMod. : Simulates Expander in debug mode • DspDebugMod : Simulates DSP in debug mode • Main Controller : Controls the system operation • Registers : Contain control data received from PCI +CTF to DSP

17. Blocks to implement: Designed till now: (on work- simulations) CTF Block Diagram CTF to DSP interface

18. Designed till now: CTF State Machine Path to implement:

19. DSP Entity Outputs: column_number– number of column digital_signals – data output samples_valid_out– the output data is valid support_changed– support change was detected Inputs: Clk_20 – 20MHz main input data clock Clk_240 – 240MHz processing clock From controller : reset – reset start– memory ready for read pause – pause the system From CTF : support – numbers of support support_num – how many support passed support_valid – support number is valid Internal FIFO: samples_from_fifo– data from fifo samples_fifo_valid– the data is valid From Main interface: samples_from_expander– input data for the expander samples_expander_valid– the data is valid From Matrix memory: memory_get – matrix row

20. Designed till now: Blocks to implement: DSP BlocksIncluding on Board Memories Block Description • MainBus : FIFO on board memory • Matrix : FIFO on board memory • Delay : FIFO on board memory • Output : FIFO on board memory • Matrix internal : RAM memory • Main Reader : Reads data from memory, simulates input from Exp. Main • Matrix Writer : Reads ‘A’ matrix from memory, writes to internal memory • Output Writer : Writes outputdata to memory • Fifo Reader : Reads inputdata from delay fifo • Main Bus Interface : Receives data from main bus & sends with low rate • CtfDebugMod. : Simulates CTF in debug mode • Main Controller : Controls the system operation • Registers : Contain control data received from PCI +DSP to CTF interface

21. Blocks to implement: Designed till now: (not yet implemented) DSP Block Diagram DSP to CTF interface

22. Designed till now: Path to implement: DSP State Machine

23. Future Aspirations Studying each group Entity’s I/O and single Debug mode operations (from Dima and Oleg) Studying Board busses, memories and communication clocks phase\skew problem (Gadi’s Project handle it) Design and Implement the communication blocks (Interface blocks) needed for the across linked FPGA’s- and the same time to be able to support groups with 1 FPGA Debug mode operation. Debug entire board+ all group’s Entity’s, we will held continuous meetings with the groups to synchronize with them and update them with the needed architecture changes. (each change they might have need to be informed and confirmed with us) Design and Implement Debug GUI (Visual C? JAVA? LabView?)- creating the test environment Improve GUI for board users

24. Gantt Chart

25. project part B (Not in the Gantt…) • Exams period B…  • Test and Debug Entire Board • Finish GUI Test Environment • Improve GUI to System controlling GUI

26. Questions?