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HMPID readout upgrade for ALICE TDR run3

HMPID readout upgrade for ALICE TDR run3. Present readout layout. Present RO scheme.

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HMPID readout upgrade for ALICE TDR run3

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  1. HMPID readout upgrade for ALICE TDR run3 g. de cataldo INFN Bari

  2. Present readout layout g. de cataldo INFN Bari

  3. Present RO scheme • The present read out scheme is based on a 3 RO Segments (Seg. 1-3) equipped with a total of 24 readout cards (RO), addressed in series,; each column is read out in parallel (ck @10MHz); the Column (or Buffer)memory cards are here named Column Control card (CC) • Each RO card reads 480 channels; • Max read out rate for a full event: ~0.9 KHZ; Seg 3 Seg 2 Seg 1 RCB TTX FPGA RO 24 CC 24 RO 16 CC 24 CC 1 RO1 CC 1 RO8 1-32 SIU/DDL 480 chs 480 chs 480 chs Column 8 Column 8 Column 1 Column 1 g. de cataldo INFN Bari

  4. New RO scheme: Very preliminary • The new read out scheme should be based on a parallel read out of the 24 columns with serial read out; • Serial read out @ 640 MHzon bipolar lines (LVDM) for each column of 480 chs; • For this scheme a new CC card(NCC) , a new RCB board (NRCB)with new FPGA have to be designed; • FEE and RO cards do not need to be modified; • An expected Max read out rate for a full event: ~ 10 KHZ seems reasonable; • The HMPID remain a triggered detector with the Busy Time as OR of the Seg 1-3 BY; • The new SIU3 (?) and TTX (?) cards selected by the collaboration, will be adopted. g. de cataldo INFN Bari

  5. Schedule funding and Institute • Schedule: as from the SIU3 and TTX(?) cards specifications are available, one year for the design and the production of the first prototype of the NCC and NRCB, is needed; • The activity of pto 1) could start as from beginning 2014; • Massive tests, debugging and commissioning of the final prototype during 2015; • Mass production of boards during 2016; • Funding: the project cost is under estimation, • Institutes: Bari INFN, CERN (to be confirmed)…and other institutions are not excluded. g. de cataldo INFN Bari

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