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第 9 章 F2812 事件管理器( EVA/B ) PowerPoint PPT Presentation


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第 9 章 F2812 事件管理器( EVA/B ). 张云洲 2010.11.26. 章节结构. 9.1 事件管理器概述 9.2 通用定时器 9.3 比较单元及 PWM 输出 9.4 捕获单元 9.5 正交编码脉冲单元 9.6 事件管理器中断. 9.1 事件管理器概述. F281x 包含两个事件管理器 EVA 和 EVB ,每个事件管理器包括通用定时器( GP )、比较器、 PWM 单元,捕获单元以及正交编码脉冲电路( QEP )。

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第 9 章 F2812 事件管理器( EVA/B )

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9 f2812 eva b

9 F2812EVA/B

2010.11.26


9 f2812 eva b

9.1

9.2

9.3 PWM

9.4

9.5

9.6


9 f2812 eva b

9.1

  • F281x EVA EVBGPPWM QEP

  • PWM : (1) (2) PWM6

  • QEP

  • EVA EVB EVA 7400HEVB 7500H


9 f2812 eva b

  • C28x

  • TCLKINATDIRAADC

  • 1 2 2T1PWM /T1CMP T2PWM/T2CMP16 DSP1 ~3 1 6 PWM 3 CAP12 3 CAP12 3


9 f2812 eva b

/

TCLKINA / TDIRA

PWM Circuits

Output Logic

PWM Circuits

Output Logic

PWM Circuits

Output Logic

GP Timer 2 Compare

Compare Unit 1

GP Timer 1 Compare

GP Timer 2

Compare Unit 2

GP Timer 1

QEP

Circuit

CLK

Compare Unit 3

DIR

MUX

CAP1/QEP1

CAP2/QEP2

CAP3/QEPI1

(EVA)

Reset

PIE

2

EV Control Registers / Logic

ADC Start

Output Logic

T1PWM_T1CMP

PWM1

PWM2

PWM3

Data Bus

PWM4

PWM5

PWM6

Output Logic

T2PWM_T2CMP

Capture Units


9 f2812 eva b

9.2

  • EVAGP1GP2EVBGP3GP4PWM3

  • GPTCONA/B

  • QEPHSPCLK


9 f2812 eva b

TCLKS 1-0

M

U

X

TxCON . 5 - 4

Shadowed

Compare

Register

Clock

Prescaler

Compare

Logic

TPS 2-0

TxCON . 10 - 8

Period

Register

Shadowed

GP

Internal

(HSPCLK)

TxCMPR . 15 - 0

TxCNT . 15 - 0

GPTCONA

TxPWM_

TxCMP

Output

Logic

16 - Bit Timer

Counter

External 1/4

QEP

Note: x = 1 or 2

TxPR . 15 - 0


9 f2812 eva b

  • = TxPR+1

GP

(Used for Asymmetric PWM Waveforms)

This example:

TxCON.3-2 = 00 ( TxCMPR)

TxPR = 3

TxCMPR = 1 (initially)

Prescale = 1

CPU writes a 2 to

compare reg. buffer

anytime here

TxCMPR=2

3

3

3

2

1

1

0

0

0

TxCNT Reg.

TxPWM/TxCMP

(active high)

CPUCLK


9 f2812 eva b

  • is 2*TxPR

TxCMPR =2

TxCMPR =1

TxCMPR =1

GP /

(Used for Symmetric PWM Waveforms)

This example:

TxCON.3-2 = 01 (==00/PR.reg)

TxPR = 3

TxCMPR = 1 (initially)

Prescale = 1

PR.reg

PR.reg

3

3

2

2

2

2

1

1

1

1

00

0

0

0

TxCNT Reg.

00

TxPWM/TxCMP

(active high)

CPUCLK


9 f2812 eva b

  • C28x12


9 2 1

9.2.1

  • ///4TxCONMODE1-TMODE0

  • TENABLEx/1TxCONTMODE1-TMODE0


9 2 2

9.2.2

1TxCMPR1PWM

TxPWM

TxCON[1]

  • CPUGPTCONA/BPWM

  • GPTCONA/BAD


9 f2812 eva b


9 f2812 eva b

PRreg=

Comp1

PRreg=

Comp2

PWM

PWM #2

TxCON.3-2= 00

PR=Comp1

2T

PWM #1

T

T

T

Comp2

Comp1

TxCMP/TxPWM

(active high)

TxCMP/TxPWM

(active low)


9 f2812 eva b

RegisterAddressDescription

GPTCONA0x007400GP A

T1CNT0x0074011

T1CMPR0x0074021

T1PR0x0074031

T1CON0x0074041

T2CNT0x0074052

T2CMPR0x0074062

T2PR0x0074072

T2CON0x0074082

GPTCONB0x007500GP B

T3CNT0x0075013

T3CMPR0x0075023

T3PR0x0075033

T3CON0x0075043

T4CNT0x0075054

T4CMPR0x0075064

T4PR0x0075074

T4CON0x0075084

EVA

EVB

GP

EXTCONA 0x007409 / EXTCONB 0x007509 ;


9 f2812 eva b

GP Timer 2 Compare

Compare Unit 1

GP Timer 2

Compare Unit 2

QEP

Circuit

Compare Unit 3

MUX

EVA

Reset

PIE

2

/

TCLKINA / TDIRA

EV Control Registers / Logic

ADC Start

Output Logic

GP Timer 1 Compare

T1PWM_T1CMP

GP Timer 1

PWM1

PWM Circuits

Output Logic

PWM2

PWM3

PWM Circuits

Output Logic

Data Bus

PWM4

PWM5

PWM Circuits

Output Logic

PWM6

Output Logic

T2PWM_T2CMP

CLK

DIR

CAP1/QEP1

Capture Units

CAP2/QEP2

CAP3/QEPI1


9 f2812 eva b

PWM

  • PWM

    • 0

  • PAM


9 f2812 eva b

t

Original Signal

t

t

T

T

PWM

PAM

PWM

same areas (energy)


Pwm motor

PWM Motor

  • PWMDSP

DC Supply

DC Supply

?

PWM

Desired

signal to

motor phase

PWM approx.

of desired signal

Unknown Gate Signal

Gate Signal Known with PWM


9 2 2 3 txpwm

9.2.2.3 TxPWM

  • /PWM

    • 0

    • PWM

    • 0

  • 010001

  • PWMPWM


9 f2812 eva b

TPWM

PWM

Period

Compare

Counter

Tpwm / Tcmp Pin

(active high)

Caused by Period match

(toggle output in Asym mode only)

Caused by Compare match


9 2 2 4 txpwm

9.2.2.4 TxPWM

  • /

    • 0

    • PWM

    • PWM

    • 00

  • 0101000%100%PWM001


9 f2812 eva b

General Purpose Timer

Full Compare Units

PWM1

Compare

Compare

Compare

Period

Compare

Counter

PWM2

PWM3

TPWM/TCMP Pin

PWM4

PWM5

PWM6

PWM

TPWM

Period

Compare

Counter

TPWM /TCMP Pin

(active high)

Interrupts


9 2 2 1 pwm txpwm

9.2.2.1 PWM TxPWM

  • PWMGPTCONA/BPWM

  • PWM/PWM/GPTCONA/BPWMPWM10

  • PWM


9 f2812 eva b


9 f2812 eva b

  • /PWM

    • GPTCONA/B[6]

    • PDPINTx

    • TxCON[1]


9 f2812 eva b

PWM


9 2 2 5

9.2.2.5

  • C28x

  • TCLKINAB

  • PWM

  • PWMT1PWM_T1CMPT2PWM_T2CMP

  • PWM/

  • PWM/

  • PWMPWM

  • PWMTxPR

  • TxCONPWM

  • PWMTxCMPR

  • PWMPWM

  • 1/

  • PWMPWM2

  • PWM

  • F2812T1PWM

  • 88

  • PWM

  • 050msCPU

  • 1

  • PWM


9 f2812 eva b

  • //************************************************************

  • //

  • // Playatune.c

  • //

  • // DSP28 T1PWMPWM,

  • // CPU 050 ms

  • //

  • //

  • //*************************************************************//

  • #include "DSP281x_Device.h"

  • //

  • void Gpio_selectvoid;

  • void SpeedUpRevAvoid;

  • void InitSystemvoid;

  • interrupt void cpu_timer0_isrvoid; // 0

  • void mainvoid

  • {

  • unsigned int i;

  • unsigned long time_stamp;

  • int frequency[8]={2219,1973,1776,1665,1480,1332,1184,1110};


9 f2812 eva b

  • InitSystem; // DSP

  • Gpio_select; // GPIO

  • InitPieCtrl; // DSP281x_PieCtrl.c

  • InitPieVectTable; // DSP281x_PieVect.c

  • 0Timer 0

  • EALLOW; //

  • PieVectTable.TINT0 = &cpu_timer0_isr;

  • EDIS; //

  • InitCpuTimers;

  • CPU050 ms:

  • CPU150MHz CPU , 50000

  • ConfigCpuTimer&CpuTimer0, 150, 50000;

  • TINT0

  • PieCtrlRegs.PIEIER1.bit.INTx7 = 1;

  • CPUINT1CPU0CPU

  • IER = 1;


9 f2812 eva b

  • //

  • EINT; // INTM

  • ERTM; // DBGM

  • EVA

  • EVAInitSysCtrl

  • T1/T2T1PWM / T2PWM

  • EvaRegs.GPTCONA.bit.TCMPOE = 1;

  • 1

  • EvaRegs.GPTCONA.bit.T1PIN = 1;

  • EvaRegs.T1CON.all = 0x1702; // T1


9 f2812 eva b

  • CpuTimer0Regs.TCR.bit.TSS = 0;

  • i = 0;

  • time_stamp = 0;

  • while1

  • {

  • if CpuTimer0.InterruptCount%4==0

  • {

  • EALLOW;

  • SysCtrlRegs.WDKEY = 0xAA; //

  • EDIS;

  • }

  • if CpuTimer0.InterruptCount - time_stamp>10

  • {

  • time_stamp = CpuTimer0.InterruptCount;

  • ifi<7 EvaRegs.T1PR = frequency[i++];

  • else EvaRegs.T1PR = frequency[14-i++];

  • EvaRegs.T1CMPR = EvaRegs.T1PR/2;

  • EvaRegs.T1CON.bit.TENABLE = 1;

  • if i>=14 i=0;

  • }

  • }

  • }


9 f2812 eva b

  • // IO

  • void Gpio_selectvoid

  • {

  • EALLOW;

  • GpioMuxRegs.GPAMUX.all = 0x0; // GPIOI/O

  • GpioMuxRegs.GPAMUX.bit.T1PWM_GPIOA6 = 1; // T1PWM

  • GpioMuxRegs.GPBMUX.all = 0x0;

  • GpioMuxRegs.GPDMUX.all = 0x0;

  • GpioMuxRegs.GPFMUX.all = 0x0;

  • GpioMuxRegs.GPEMUX.all = 0x0;

  • GpioMuxRegs.GPGMUX.all = 0x0;

  • GpioMuxRegs.GPADIR.all = 0x0; // GPIO PORT

  • GpioMuxRegs.GPBDIR.all = 0x00FF; // GPIO Port B15-B8 , B7-B0

  • GpioMuxRegs.GPDDIR.all = 0x0; // GPIO PORT

  • GpioMuxRegs.GPEDIR.all = 0x0; // GPIO PORT

  • GpioMuxRegs.GPFDIR.all = 0x0; // GPIO PORT

  • GpioMuxRegs.GPGDIR.all = 0x0; // GPIO PORT

  • GpioMuxRegs.GPAQUAL.all = 0x0; // GPIO0

  • GpioMuxRegs.GPBQUAL.all = 0x0;

  • GpioMuxRegs.GPDQUAL.all = 0x0;

  • GpioMuxRegs.GPEQUAL.all = 0x0;

  • EDIS;

  • }


9 f2812 eva b

  • //

  • void InitSystemvoid

  • {

  • EALLOW;

  • SysCtrlRegs.WDCR= 0x00AF; //

  • // 0x00E8 Prescaler = 1

  • // 0x00AF Prescaler = 64

  • SysCtrlRegs.SCSR = 0; // RESET

  • SysCtrlRegs.PLLCR.bit.DIV = 10; // 5

  • SysCtrlRegs.HISPCP.all = 0x1; // 2

  • SysCtrlRegs.LOSPCP.all = 0x2; // 4

  • //

  • SysCtrlRegs.PCLKCR.bit.EVAENCLK=1;

  • SysCtrlRegs.PCLKCR.bit.EVBENCLK=0;

  • SysCtrlRegs.PCLKCR.bit.SCIAENCLK=0;

  • SysCtrlRegs.PCLKCR.bit.SCIBENCLK=0;

  • SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0;

  • SysCtrlRegs.PCLKCR.bit.SPIENCLK=0;

  • SysCtrlRegs.PCLKCR.bit.ECANENCLK=0;

  • SysCtrlRegs.PCLKCR.bit.ADCENCLK=0;

  • EDIS;

  • }


9 f2812 eva b

  • // CPU0

  • interrupt void cpu_timer0_isrvoid

  • {

  • CpuTimer0.InterruptCount++;

  • //

  • EALLOW;

  • SysCtrlRegs.WDKEY = 0x55; // Serve watchdog #1

  • EDIS;

  • //

  • PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

  • }


9 2 3

9.2.3

  • 5


9 2 3 1

9.2.3.1

  • GPTCONA/BBGTPCONBGTPCONAGTPCONA12GTPCONB34


9 f2812 eva b

  • 1413107

  • ADC612

  • 9.4


9 2 3 2 txcnt x 1 2 3 4

9.2.3.2 TxCNTx=1,2,3,4


9 2 3 3 txcmpr x 1 2 3 4

9.2.3.3 TxCMPRx=1,2,3,4


9 2 3 4 txpr x 1 2 3 4

9.2.3.4 TxPRx=1,2,3,4


9 2 3 5 txcon

9.2.3.5 TxCON

  • 1514JTAG


9 f2812 eva b

  • 12~11108

  • 30MHz

  • PLLPLLCR10/2 = 150 MHz

  • HISPCP = 2= 75 MHz

  • 1128

  • 100ms

  • 1/*1/PLL*HISPCP*

  • 1,7067 s 1/ 30 MHz *1/5 * 2 * 128

  • 100 ms / 1,7067 s 58593.

  • TxPR58593100ms

  • 61

  • 54321

  • 702T1CON7

  • 129.8


9 3 pwm

9.3 PWM

  • 9.3.1

  • EVA3123EVB

  • 3456PWM

  • 13PWM

  • PWM9.14


9 f2812 eva b

2

+

PWM

DC

-


9 f2812 eva b

supply rail

PWM

to motor phase

  • -


9 f2812 eva b

DBTCONA . 11 - 8

DBTCONA . 4 - 2

Clock

PHx

DT

DTPHx

DTPHx_

PWM

(EVA)

Prescaler

HSPCLK

PHx

edge

detect

ENA

4-bit

Counter

reset

comparator

DT

4-bit period

DTPHx

DTPHx_


Eva dbtcona @ 0x007415

(EVA)DBTCONA @ 0x007415

dead time = DB period * DB prescaler * CPUCLK period

DB Timer Period

15

14

13

12

11

10

9

8

DBT3

DBT2

DBT1

DBT0

reserved

reserved

reserved

reserved

7

6

5

4

3

2

1

0

EDBT3

EDBT2

EDBT1

DBTPS2

DBTPS1

reserved

reserved

DBTPS0

DB Timer Prescaler

000 = 1100 = 16

001 = 2101 = 32

010 = 4 110 = 32

011 = 8 111 = 32

DB Timer Enable

0 = disable

1 = enable


9 f2812 eva b

  • 1T1CNT

  • CMPRx

  • PWMT1CNTCMPRxPWM


9 f2812 eva b

  • Action Control Register ACTRA

  • COMCONAPWM

  • 6PWM

  • T1CNTCMPRxPWM01

  • PWM10

  • T1CNTCMPRxPWM10

  • PWM01

  • PWM1

  • PWM0


9 3 2 pwm

9.3.2 PWM

  • PWM

  • PWMPWM

  • PWM

  • PWMPWM

  • PWMPWM


9 f2812 eva b

  • PWM

  • PWMPWMPWMPWMNPNPNP9.17


9 f2812 eva b

  • On: Ice =

  • Icesat, Off: Ice = 0


9 3 3 pwm

9.3.3 PWM

  • 9.18EVAPWM

  • /

  • DBU

  • SV PWM

  • EVBPWMEVA

  • /


Eva pwm

EVAPWM


9 f2812 eva b

  • C28xPWMCPUPWMPWMEVAT1CONCOMCONAACTRA DBTCONAEVBT3CONCOMCONBACTRB DBTCONBEVAEVBPWMPWM

  • 5PWM32

  • 3PWM

  • PWM

  • CPU

  • CPUCPU

  • PWM16

  • PWM

  • PWM

  • PWM

  • CPU


9 3 4 pwm

9.3.4 PWM

9.3.4.1 PWM

  • PWMxx = 112ACTRPWMPWM

  • COMCONx[9]

  • PDPINTx PDPINTx

  • PDPINTx COMCONxACTRx


9 f2812 eva b

  • 9.19OLC

  • DTPH1DTPH1 DTPH2DTPH2DTPH3DTPH3

  • ACTRx

  • PDPINTx

  • PWMxx = 16 EVA

  • PWMyy = 712 EVB

  • ACTRx[01, 23, . . . or 1011]


9 3 4 2

9.3.4.2

  • /PWMDTPHxDTPHx

  • PWMFETPWM


9 f2812 eva b

  • PWM

  • PWMC28xCPU

  • EVAEVBDBTCONADBTCONB

  • 16DBTCONx

  • 16x/1x/2x/4x/8x/16x/32

  • CPU

  • 34


9 f2812 eva b

  • 123/PH1PH2PH3DTPH1DTPH1_DTPH2DTPH2_DTPH3 DTPH3_PH1PH2 PH3PHxDTPHxDTPHx_DBTCONxDBTCONx[118]mDBTCONx[42]x/p p*m HSPCLK


9 3 4 pwm1

9.3.4 PWM

  • PWMPWMPWMPWM

  • EVPWM3PWMPWMPWMPWMPWMCOMCONxPWMDBTCONx11:8DBT3:04PWM

  • ACTRxPWMPWMPWMPWMPWM


9 3 4 1 pwm

9.3.4.1 PWM

  • 13PWM

  • PWM

  • PWM

  • PWM


9 f2812 eva b

  • PWMPWMCOMCONxPWMDBTCONx11:8DBT3:04PWM


9 3 4 2 pwm

9.3.4.2 PWM

  • PWMPWMPWMPWMPWM

  • PWMPWMPWM


9 f2812 eva b

PWM


9 f2812 eva b

  • PWMPWM13/PWMPWMPWMPWMPWM


9 3 4 3 svpwm

9.3.4.3 SVPWM

  • EVPWMPWMPWM

  • ACTRx

  • COMCONxPWMCMPRx

  • 1 3/

  • d-qUoutUoutPWM

  • UxUx+60

  • T1T2T0

  • UxACTRx[1412]1ACTRx[15]

  • Ux+60ACTRx[1412]0ACTRx[15]

  • 1/2 T11/2 T1 + 1/2 T2CMPR1CMPR2


1 pwm

1PWM

  • PWMEVPWM

  • UyACTRx[1412]PWM

  • CMPR111/2T1

  • ACTRx[15]1PWMUy+60ACTRx[15]

  • 0PWMUyU0-60=U300U360+60=U60

  • CMPR211/2 T1 + 1/2 T2

  • PWM0001111

  • CMPR211/2 T1 + 1/2 T2

  • PWM

  • CMPR111/2T1

  • PWM


2 pwm

2PWM

  • PWMPWMPWM

  • 9.25


9 3 4 4 svpwm

9.3.4.4 SVPWM

  • // EVT1PWM, T2PWM, T3PWM, T4PWM PWM1-12

  • // DSP28_EvPwm.c

  • //********************************************************

  • #include "DSP28_Device.h"

  • void mainvoid

  • {

  • // Step 1PLL

  • InitSysCtrl;

  • // Step 2GPIO

  • EALLOW;

  • // PWM

  • GpioMuxRegs.GPAMUX.all = 0x00FF; // EVA PWM 1-6

  • GpioMuxRegs.GPBMUX.all = 0x00FF; // EVB PWM 7-12

  • EDIS;

  • // Step 3PIE vector table:

  • // CPU

  • DINT;

  • IER = 0x0000;

  • IFR = 0x0000;

  • // Pie

  • InitPieCtrl;

  • //PIE

  • InitPieVectTable;


9 f2812 eva b

  • // Step 3EVAT1PWM, T2PWM, PWM1-PWM6

  • //

  • // EVA1

  • EvaRegs.T1PR = 0xFFFF; //1

  • EvaRegs.T1CMPR = 0x3C00; //1

  • EvaRegs.T1CNT = 0x0000; //1

  • // TMODE =/

  • EvaRegs.T1CON.all = 0x1042;

  • //EVA2

  • EvaRegs.T2PR = 0x0FFF; //2

  • EvaRegs.T2CMPR = 0x03C0; //2

  • EvaRegs.T2CNT = 0x0000; //2

  • // TMODE =/

  • EvaRegs.T2CON.all = 0x1042;


9 f2812 eva b

  • // T1PWMT2PWM

  • // T1/T2 PWM

  • EvaRegs.GPTCONA.bit.TCOMPOE = 1;

  • //1

  • EvaRegs.GPTCONA.bit.T1PIN = 1;

  • //2

  • EvaRegs.GPTCONA.bit.T2PIN = 2;

  • // PWM1-PWM6

  • EvaRegs.CMPR1 = 0x0C00;

  • EvaRegs.CMPR2 = 0x3C00;

  • EvaRegs.CMPR3 = 0xFC00;

  • //

  • // 1 CMPR1

  • // 2 CMPR1

  • // 3 CMPR2

  • // 4 CMPR2

  • // 5 CMPR3

  • // 6 CMPR3

  • EvaRegs.ACTRA.all = 0x0666;

  • EvaRegs.DBTCONA.all = 0x0000; //

  • EvaRegs.COMCONA.all = 0xA600;


9 f2812 eva b

  • // Step 4EVBT3PWM, T4PWMPWM7-PWM12

  • //

  • // EVB3

  • // 3T3PWMPWM7-12

  • EvbRegs.T3PR = 0xFFFF; // 3

  • EvbRegs.T3CMPR = 0x3C00; // 3

  • EvbRegs.T3CNT = 0x0000; // 3

  • // TMODE =/

  • EvbRegs.T3CON.all = 0x1042;

  • // EVB4

  • // 4T4PWM

  • EvbRegs.T4PR = 0x00FF; // 4

  • EvbRegs.T4CMPR = 0x0030; // 4

  • EvbRegs.T4CNT = 0x0000; // 3

  • // TMODE =/

  • EvbRegs.T4CON.all = 0x1042;

  • // T3PWMT4PWM

  • // T3/T4 PWM

  • EvbRegs.GPTCONB.bit.TCOMPOE = 1;

  • //3

  • EvbRegs.GPTCONB.bit.T3PIN = 1;

  • //4

  • EvbRegs.GPTCONB.bit.T4PIN = 2;


9 f2812 eva b

  • // PWM7-PWM12

  • EvbRegs.CMPR4 = 0x0C00;

  • EvbRegs.CMPR5 = 0x3C00;

  • EvbRegs.CMPR6 = 0xFC00;

  • //

  • // 1 CMPR4

  • // 2 CMPR4

  • // 3 CMPR5

  • // 4 CMPR5

  • // 5 CMPR6

  • // 6 CMPR6

  • EvbRegs.ACTRB.all = 0x0666;

  • EvbRegs.DBTCONB.all = 0x0000; //

  • EvbRegs.COMCONB.all = 0xA600;

  • // Step 5 IDLE

  • // PWM

  • for;;;

  • }


9 3 5

9.3.5


9 3 5 1

9.3.5.1


9 f2812 eva b


9 3 5 2

9.3.5.2


9 3 5 3

9.3.5.3


9 3 5 3 ev

9.3.5.3 EV

  • EXTCONAEXTCONB/EXTCONx240xAB9.289.13EVA


9 f2812 eva b

9.4

  • 9.4.1

  • A3122FIFO3ADAD


9 f2812 eva b

GP Timer 1 Compare

GP Timer 1

PWM Circuits

Output Logic

PWM Circuits

Output Logic

PWM Circuits

Output Logic

GP Timer 2 Compare

Compare Unit 1

GP Timer 2

Compare Unit 2

QEP

Circuit

Compare Unit 3

(EVA)

Reset

PIE

2

/

TCLKINA / TDIRA

EV Control Registers / Logic

ADC Start

Output Logic

T1PWM_T1CMP

PWM1

PWM2

PWM3

Data Bus

PWM4

PWM5

PWM6

Output Logic

T2PWM_T2CMP

CLK

MUX

DIR

CAP1/QEP1

Capture Units

CAP2/QEP2

CAP3/QEPI1


9 f2812 eva b

  • Can latch on:

    • rising edge

    • falling edge

    • both

T1CNT . 15 - 0

T2CNT . 15 - 0

GP Timer 1

Counter

GP Timer 2

Counter

MUX

CAPCONA . 10 - 9

CAPCONA . 8

CAPCONA . 7 - 2

CAPFIFOA . 13 - 8

CAPCONA . 14 -12

CAPCONA . 15

TTL Signal

min. valid width:

2 CPUCLK lo

2 CPUCLK hi

(EVA)

CAP3TOADC

Enable

.

ADC Start

(CAP 3)

Edge

Detect

3

/

CAP1,2,3

Edge Select

2-Level Deep

RS

FIFO

CAPRESET

CAPxFIFO Status


9 f2812 eva b

?

/4

/4

LED

Ch. A

Ch. B

shaft rotation

Quadrature Output from Photo Sensors

Incremental Optical Encoder


9 f2812 eva b

PWM Circuits

Output Logic

PWM Circuits

Output Logic

PWM Circuits

Output Logic

GP Timer 2 Compare

Compare Unit 1

GP Timer 1 Compare

GP Timer 2

Compare Unit 2

GP Timer 1

Compare Unit 3

MUX

(EVA)

Reset

PIE

2

/

TCLKINA / TDIRA

EV Control Registers / Logic

ADC Start

Output Logic

T1PWM_T1CMP

PWM1

PWM2

PWM3

Data Bus

PWM4

PWM5

PWM6

Output Logic

T2PWM_T2CMP

CLK

QEP

Circuit

DIR

CAP1/QEP1

Capture Units

CAP2/QEP2

CAP3/QEPI1


9 f2812 eva b

10

00

11

01

?

Position resolution is /4 degrees.

increment

counter

decrement

counter

(00)

(11)

(A,B) =

(10)

(01)

Quadrature

Decoder

State Machine

Ch. A

Ch. B


9 f2812 eva b

(EVA)

Ch. A

  • GP Timer 2 selected as pulse counter

  • Timer Prescaler bypassed (i.e. Prescale always 1)

.

Ch. B

CAP1/QEP1

QEP

decoder

logic

.

CAP2/QEP2

Index

CLK

DIR

CAP3/QEPI

QEPIQUAL

QEPIE

GP Timer 2


9 f2812 eva b

  • AD3


9 4 2

9.4.2

  • 416CAPCONA/BCAPFIFOA/BTxCON x = 1, 2, 34

  • 16 EVACAPCONAEVBCAPCONB

  • 16FIFOEVACAPFIFOAEVBCAPFIFOB

  • 12EVA34EVB

  • 6162FIFO

  • 6CAP1CAP6

  • CPU

  • CPU

  • CAP1CAP2EVBCAP4CAP5QEP

  • 61


9 4 3

9.4.3

  • FIFOFIFOCAPxFIFO0

  • FIFOFIFOCAPFIFOx

  • FIFO

  • 2CPU0


9 f2812 eva b

  • 9.4.3.1

  • EVA312

  • 12131EVB

  • 6

  • /PWM

  • CAPFIFOx

  • CAPCONACAPCONB


9 4 3 2 fifo

9.4.3.2 FIFO

  • FIFOCAP1FIFOCAP2FIFO CAP3FIFO EVACAP4FIFOCAP5FIFOCAP6FIFO EVBCAP1FBOTCAP2FBOTCAP3FBOT EVACAP4FBOTCAP5FBOTCAP6FBOTEVBFIFOFIFOFIFO

  • FIFOFIFOFIFO011011FIFO01FIFOFIFO00


9 f2812 eva b

  • 1

  • FIFO01FIFOFIFO00

  • 2

  • 10FIFO01

  • 3

  • FIFOFIFO111


9 4 3 2

9.4.3.2

  • FIFOCAPxFIFO

  • 0


9 4 4

9.4.4


9 4 4 1

9.4.4.1


9 4 4 12

9.4.4.12

  • FIFOCAP1FIFOCAP2FIFO CAP3FIFO EVACAP4FIFOCAP5FIFOCAP6FIFO EVBCAP1FBOTCAP2FBOTCAP3FBOT EVACAP4FBOTCAP5FBOTCAP6FBOTEVB

  • FIFOFIFOFIFO

  • FIFOFIFOFIFO011011FIFO01FIFOFIFO00


9 f2812 eva b

  • FIFOCAPFIFOAFIFO

  • FIFO

  • 01FIFO

  • FIFO00

  • 10FIFO

  • 01

  • FIFO

  • FIFO111


9 5 qep

9.5 QEP

  • 9.5.1

  • 9.34

  • 90


9 5 2 qep

9.5.2 QEP

  • QEPQEPCAP1/QEP1CAP2/QEP2 EVACAP4/QEP3CAP5/QEP4 EVBQEP

  • QEPCAP1/CAP2CAP4/CAP5

  • QEP 9.35 ABA B 4 QEP


9 f2812 eva b

  • 3QEP123456CAPCONx


9 5 3 qep

9.5.3 QEP

  • 2EVB4QEPQEP/9.37EVAQEP9.38EVBQEP


9 5 4 qep

9.5.4 QEP

  • 1/4900


9 5 4 1 qep

9.5.4.1 QEP

  • EVQEP24CAP1/QEP1 EVBCAP4/QEP3CAP2/QEP2

  • EVBCAP5/QEP4

  • QEP24424


9 5 4 2 qep

9.5.4.2 QEP

  • 24QEP

  • QEPTDIRA/B

  • TCLKINA/BQEP


9 5 5 qep

9.5.5 QEP

  • EVAQEP

  • 2

  • T2CON2/QEP

  • CAPCONA

  • EVBQEP

  • 4

  • T4ON2/QEP

  • CAPCONB


9 5 6 qep

9.5.6 QEP

  • LEDLED0

  • 10241AB

  • TMS320F2812QEP

  • QEPT3CNTQEP QEP

  • T39.40


9 f2812 eva b

  • 1024 1 QEP 4096

  • QEP

  • T3CNTT3CNT QEP FFFFh T3


9 f2812 eva b

360


Tms320f2812 qep

TMS320F2812 QEP

  • //******************************************************************************

  • // F28XQEP.C

  • //******************************************************************************

  • #include "DSP28_Device.h"

  • #include "f28xqep.h"

  • #include "f28xbmsk.h"

  • void F28X_EV1_QEP_InitQEP *p

  • {

  • EvaRegs.CAPCON.all = QEP_CAP_INIT_STATE; /* */

  • EvaRegs.T2CON.all = QEP_TIMER_INIT_STATE; /**/

  • EvaRegs.T2PR = 0xFFFF;

  • EvaRegs.EVAIFRC.bit.CAP3INT = 1; /*CAP3 */

  • EvaRegs.EVAIMRC.bit.CAP3INT = 1; /*CAP3 */

  • GpioMuxRegs.GPAMUX.all |= 0x0700; /**/

  • }


9 f2812 eva b

  • void F28X_EV1_QEP_CalcQEP *p

  • {

  • long tmp;

  • p->dir_QEP = 0x4000&EvaRegs.GPTCONA.all;

  • p->dir_QEP = p->dir_QEP>>14;

  • p->theta_raw = EvaRegs.T2CNT + p->cal_angle;

  • tmp = longp->theta_raw*p->mech_scaler; /* Q0*Q26 = Q26 */

  • tmp &= 0x03FFF000;

  • p->theta_mech = inttmp>>11; /* Q26 -> Q15 */

  • p->theta_mech &= 0x7FFF;

  • p->theta_elec = p->pole_pairs*p->theta_mech; /* Q0*Q15 = Q15 */

  • p->theta_elec &= 0x7FFF;

  • }

  • void F28X_EV1_QEP_IsrQEP *p

  • {

  • p->QEP_cnt_idx = EvaRegs.T2CNT;

  • EvaRegs.T2CNT = 0;

  • p->index_sync_flag = 0x00F0;

  • }


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