html5-img
1 / 34

Computer architecture

Computer architecture. Lecture 11: Reduced Instruction Set Computers Piotr Bilski. Characteristics of the RISC architecture. Processor contains large number of the general purpose registers RISC compilers use procedures for the register usage optimization

fayola
Download Presentation

Computer architecture

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Computer architecture Lecture 11: Reduced Instruction Set Computers Piotr Bilski

  2. Characteristics of the RISC architecture • Processor contains large number of the general purpose registers • RISC compilers use procedures for the register usage optimization • Number of the instructions is small in comparison with CISC architecture • Instructions have basic structure • Instruction pipeline is optimized

  3. Comparison between the selected processors

  4. RISC and the programming languages • High-level language – alleviations for the programmer, multiple hidden details • Necessity to translate high-level language into the machine language • Small high-level programs  large machine programs • Increase of the effectiveness requires construction of the complex compilers

  5. Characteristics of the executed instructions • Instruction types – instructions executed by the processor • Types and number of the instruction arguments • Instruction scheduling – pipelining

  6. Analysis of the frequency of the executed instructions [%]

  7. Analysis of the frequency of the executed instructions (cont.)

  8. Arguments processed by the instructions

  9. Exploitation of the arguments in the procedure calls

  10. Register tables • Requirement for the assignment operations optimization – registers • Local variables should be stored in one register block • Problem of passing arguments to funcions and returning variables • Nested function calls and the number of the registers

  11. Register windows • Functions use small number of the local variables, so every function requires small number of registers • Every function has different set of the registers assigned (so-called window) • Neighbor windows overlap, allowing to pass arguments between functions

  12. Parameter registers Parameter registers Local registers Local registers Temporary registers Temporary registers Register windows - organization level I Call/return level I+1

  13. Window registers - example • Current window pointer (CWP) • Saved window pointer (SWP)

  14. Global variables • Handled by the global registers set • Problem of the global register addressing in the window – uniform addressing mode • Decision about assignment of the variables to the register depends on the compiler

  15. Registers table and cache

  16. Registers table and cache (cont.) a) Instruction Data R Row number Decoder b) Instruction A Data Pointers Data comparison

  17. Register olptimization using compiler • For the small number of registers, decision must be made, which variables should be assigned to them • An infinite number of the symbolic registers is created, which are further mapped onto the real registers • Assignment is the graph coloring problem

  18. Graph coloring example 2 3 • Vertices are symbolic registers • Colors are real registers 1 4 Register interference 5 6

  19. Problems of the compiler design • Does smaller program mean smaller machine code? • Are programs containing more complex procedures faster?

  20. RISC instruction characteristics • One instruction executed during the cycle • Data transfer operations „from register to register” • Only simple addressing modes • Simple instruction formats

  21. RISC machine instruction • One instruction during one machine cycle • Machine cycle is the time required to fetch two arguments from registers, performing ALU operation and storing result into the register • no microcode, instruction executed by the hardware!

  22. Data transfer register-register • All data should be in registers • Exceptions are memory references (LOAD, STORE) • Smaller instruction list, simpler control unit 8 16 16 16 8 4 4 4 Instruction size = 168 B Instruction size= 60 B

  23. Simple instruction formats • All instructions have constant size! • Simple instructions are easier to optimize during compilation • ALU for the simpler instructions is simpler and faster • Pipelining is more effective • Easier interrupt handling • The most frequently executed instructions can be implemented in the hardware

  24. CISC vs RISC

  25. Pipelining • Register-to-register processing • Instruction fetching (F) • Instruction execution (E) • Loading and writing into memory • Instruction fetching (F) • Instruction execution (E) • Memory operation (M)

  26. F E M F E M F E M F E M F E M F E M F E M Sequential operation and pipelining

  27. F E M F E M F E M F E F E1 E2 M F E1 E2 M Pipelining • 2-stage – one memory access • 3-stage – two memory accesses • 4-stage F E M E M F

  28. F E M F E M F F E F E Pipelining with branch • Program: • LOAD X,A • ADD 1,A • JUMP 105 • ADD A,B • SUB C,B • STORE A,Z 1 2 3 4 5 6 7 8

  29. F E M F E M F E F E F E Insertion of the empty instruction • Program: • LOAD X,A • ADD 1,A • JUMP 106 • NOOP • 106 STORE A,Z 1 2 3 4 5 6 7 8

  30. F E M F E M F E F E Reversed instruction sequence • Program: • LOAD X,A • JUMP 105 • ADD 1,A • 105 STORE A,Z 1 2 3 4 5 6 7 8

  31. RISC example – MIPS R4000 • 64-bit architecture processor (with such registers and ALU bus) • In the R4000 there is one processor and one Memory Management Unit – MMU • 32 general purpose registers, up to 128 kB of the cache memory (half for the instructions and data) • Constant instruction format – 4 bytes • No conditional codes • Three instruction formats

  32. MIPS R4000 instruction formats 6 5 5 16 Operation with the immediate operand branch Register addressing Operation rs rt Immediate 6 26 Operation Target 6 5 5 5 5 6 Operation rs rt rd offset function

  33. RISC example – Sun SPARC • processor uses register windows (2 to 32 windows 24 registers each) • Eight global registers (0-7) • Output registers (called with the called procedure, 8-15) • Input registers (used with the calling procedure, 24-31) • Local registers, labelled with 16-23 • All instructions 32-bit long

  34. SPARC instruction formats 2 30 call branch SETHI Floating point format Generic format Op relative shifting of the program counter 2 1 4 3 22 Op a cond. op2 rel. shift. of the progr. Count. 2 5 3 22 Op Target op2 Immediate constant 2 5 6 5 9 5 Op Target Op3 Src-1 FP-op Src-2 2 5 6 5 1 8 5 Op Target Op3 Src-1 0 dism. Src-2 2 5 6 5 1 13 Op Target Op3 Src-1 1 Imm. constant

More Related