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Technical Report. High Speed CMOS A/D Converter Circuit for Radio Frequency Signal. Kyusun Choi. Computer Science and Engineering Department The Pennsylvania State University. Project Goals. Core development and silicon test of 6 and 8 bit TIQ based flash ADC.

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slide1

Technical Report

High Speed CMOS A/D Converter Circuit for

Radio Frequency Signal

Kyusun Choi

Computer Science and Engineering Department

The Pennsylvania State University

slide2

Project Goals

Core development and silicon test of

6 and 8 bit TIQ based flash ADC

  • High speed circuit and layout design
  • 2. Prototype chip fabrication
  • 0.25um and 0.18um CMOS
  • 3. Test and evaluate, explore and improve
slide3

Project Milestones

  • 1st Chip design, 0.25um 12/01/2000
  • Chip fabrication 02/05/2001
  • Chip testing 04/04/2001 1st report
  • 2nd chip design, 0.18um 07/10/2001 2nd report, chip
  • Chip fabrication 10/08/2001
  • Chip testing 11/09/2001 3rd report
  • Project ending 12/31/2001 Chip
  • Project presentation 02/15/2002 Final report
slide4

Project Feature

  • High speed ADC, 1 GSPS
  • RF applications
  • SOC applications, digital CMOS
  • Future-ready, < 0.10um, < 1.0V
slide5

gain booster

V1

Vin

gain booster

V2

D1

D2

gain booster

D3

V3

Dk

gain booster

circuit

gain booster

Vn

Thermometer code to

binary encoder

TIQ flash ADC

slide6

Other flash ADC

Vref

V1

+

Vin

R

V2

V1

+

R

D1

D2

V3

V2

D3

+

R

V3

Dk

+

R

Vn

Vn

Thermometer code to

binary encoder

Resistor ladder

circuit

slide7

_

+

Vin

Vout

Vin

Vm

Vout

Vr

Vout

Vout

Vr

Vin

Vm

Vin

TIQ comparator

DIFFERENTIAL INPUT

VOLTAGE COMPARATOR

INVERTER

Vr is provided by a voltage references source,

External to the voltage comparator

Vm is an internal parameter of an inverter,

fixed by the transistor sizes

slide8

TIQ comparator

  • High speed
  • Less area
  • No resistor ladder and reference voltages
  • No capacitor switching
  • Future ready
      • Scale down
      • Low supply voltage
      • Standard digital logic technology
      • Ideal for SOC
slide9

Prototype Test Results

1st prototype chip (0.25um), six ADCs on chip

slide10

Prototype Test Results

2nd prototype chip (0.18um), ten ADCs on chip

slide11

Prototype Test Results

ADC: 6 bit 1.00um, ROM, 0.18um prototype chip

Input: 100 KHz Saw wave

slide12

Prototype Test Results

ADC: 6 bit 1.00um, FAT, 0.18um prototype chip

Input: 100 KHz Saw wave

slide13

Prototype Test Results

ADC: 9 bit 1.00um, ROM, 0.25um prototype chip

Input: 100 KHz Saw wave

slide14

Prototype Test Results

ADC: 6 bit 1.00um, FAT, 0.18um prototype chip

Input: DC

DNL = 0.36 LSB INL = 1.36 LSB

slide15

Prototype Test Results

ADC: 6 bit 1.00um, FAT, 0.18um prototype chip

Input: 80KHz sign wave, f_sample = 10 MHz

SNR = 23.40 dB

SNDR = 21.83 dB

SFDR = 9.13 dB

ENOB = 3.33 bits

slide16

Prototype Test Results

ADC: ideal 6 bit

Input: 1MHz sign wave, f_sample = 200 MHz

SNR = 37.78 dB

SNDR = 36.56 dB

SFDR = 37.86 dB

ENOB = 5.78 bits

slide17

Summary

  • High speed ADC for RF application
  • ADC core - 6 and 8 bit design
    • prototype chips (silicon test)
    • 0.25 m and 0.18 m
    • CMOS digital logic technology
  • SOC beyond 0.10um & 1.00V
slide18

Innovation/enhancement challenges

  • 1 GSPS with digital CMOS
  • Custom layout generation and
  • modeling CAD tool
  • 8bit and 10bit ADC
  • Low power
  • Low noise
  • Dynamic calibration
    • Offset
    • Gain
    • Temperature
    • Power supply voltage
    • Process parameter variation
slide19

Summary

  • High speed ADC for RF application
  • ADC core - 6 and 8 bit design
    • prototype chips (silicon test)
    • 0.25 m and 0.18 m
    • CMOS digital logic technology
  • SOC beyond 0.10um & 1.00V
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