1 / 32

C ombinationality checking of cyclic circuits

C ombinationality checking of cyclic circuits. Wan-Chen Weng Date: 2014/03/03. Outline. Motivation Problem formulation Combinationality Methodology Outer and Inner Side Input Loop back tracing Program flow Future work. Motivation (1/4). S. Malik (1994)

fagan
Download Presentation

C ombinationality checking of cyclic circuits

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Combinationality checking of cyclic circuits Wan-Chen Weng Date: 2014/03/03

  2. Outline • Motivation • Problem formulation • Combinationality • Methodology • Outer and Inner Side Input • Loop back tracing • Program flow • Future work

  3. Motivation(1/4) • S. Malik (1994) • For the analysis of cyclic circuits. • Let  denote the unknown value. • A voltage value between logical 0 and 1. • A signal that might be 0 or 1 but we don’t know which.

  4. Motivation(2/4) • Marc D. Riedel (2008) • SAT-based dual-rail model checking for the combinationality of cyclic circuits. • Add dummy variables and equivalent checkers to the corresponding module.

  5. Motivation(3/4) • Marc D. Riedel (2008) • The original circuit will be combinational when SAT = 0.

  6. Motivation(4/4) • Dual-rail model • checks the combinationality of cyclic circuits in a more elegant way. • still consumes memories and is the bottleneck when the circuit size is large.

  7. Combinationality(1/8) • Stephen A. Edwards (2003) • An SCC is combinational at least one input to a gate is controlling value (CV). • SCC is combinational = every loop in the SCC is false • SCC is combinational every loop in the SCC is false. • every loop in the SCC is false SCC is combinational.

  8. Combinationality(2/8) Loop with unknown signals SCC • An SCC is combinational • By definition of combinational behavior, every gate outputs a definite value. • Initially, outputs of gates from an SCC are simulated as unknown.

  9. Combinationality(3/8) CV Loop with unknown signals false loop SCC SCC • An SCC is combinational • Base case 1: • If # of loops = 1 and only 1 controlling external input

  10. Combinationality(4/8) CV CV CV L1 L2 L1 L1 L2 L2 SCC SCC SCC • An SCC is combinational • Base case 2: • If # of loops = 2 and 1 controlling external input

  11. Combinationality(5/8) CV CV CV L1 ~ Lk Lk+1 L1 ~ Lk Lk+1 L1 ~ Lk Lk+1 SCC SCC SCC • An SCC is combinational • Assume # of loops = k holds, then # of loops = k+1:

  12. Combinationality(6/8) • An SCC is combinational • By induction, every loop is false. • SCC is combinational every loop in the SCC is false.

  13. Combinationality(7/8) • Every loop in the SCC is false • Initially, internal signals of every loop are unknown. at least one side input of every loop is CV. Every gate in any loop outputs a definite value. Every gate in the SCC outputs a definite value. SCC is combinational. • Every loop in the SCC is false SCC is combinational.

  14. Combinationality(8/8) • Every loop in the SCC is false SCC is combinational. • SCC is non-combinational at least one loop is true. • SCC is combinational every loop in the SCC is false. • Exists a true loop in the SCC SCC is non-combinational.

  15. Problem formulation(1/1) • Given: • a cyclic circuit C. • Determine: • if C is combinational. • By using: • SAT-based approaches describing non-combinational relations between nodes in SCCs. • If: • SAT, then at least one true loop exists. non-combinational • UNSAT, then all loops are false. combinational

  16. Outer and Inner Side Input (1/5) A L1 B S1 n3 n1 n1 A L2 n1 n4 n4 n4 n2 n2 n2 B B n3 n3 C C

  17. Outer and Inner Side Input (2/5) • For S1being combinational: • Candidates: A, B,C. • For L1 being false: • Candidates: A, B, n3. • For L2being false: • Candidates: B, C, n1. More candidates, more chances to break loops. 17

  18. Outer and Inner Side Input (3/5) • Distinguish between external inputs and internal signals: • Outer side inputs (OSIs): • side inputs entirely from somewhere outside the SCC. • A, B, C. • Inner side inputs (ISIs): • side inputs from somewhere inside the SCC. • n1, n3. 17

  19. Outer and Inner Side Input (4/5) • (OSIx_1∧ … ∧OSIx_n∧ ISIx_1∧ … ∧ISIx_n) • = (NCV ∧ … ∧NCV ∧NCV ∧ … ∧NCV) • (loopy_1∨ …∨loopy_x∨ … ∨ loopy_n) = SAT • Non-combinational relations: • For a loop Lx: • For an SCCy:

  20. Outer and Inner Side Input (5/5) • Problems remain: • How to check if ISIs are definite? • What relation can judge oscillations between logical 0 and 1?

  21. Loop back tracing (1/10) Clause of the loop (OSIs/ISIs): (A ∧ B) Clause of n1, n2: n1 = A‧n2 (A∨n2∨n1)∧ (A∨n1) ∧ (n2∨n1) n2 = B‧n1 (B∨n1∨n2)∧ (B∨n2) ∧ (n1∨n2) Results: [SAT] (n1, n2) = (0, 0) or (1, 1) n2 A B n1

  22. Loop back tracing (2/10) Clause of the loop (OSIs/ISIs): (A ∧ B) Clause of n1, n2: n1 = A‧n2 (A∨n2∨n1)∧ (A∨n1) ∧ (n2∨n1) n2 = B‧n1 (B∨n1∨n2)∧ (B∨n2) ∧ (n1∨n2) Results: [UNSAT] n2 A B n1

  23. Loop back tracing (3/10) In fact: if (A, B) = (NCV, NCV) then (n1, n2) = (1/0, 0/1) or (n1, n2) = (0/1, 1/0). Which means: n1 and n2 always toggletheir value in the same input assignment. n2 A B n1

  24. Loop back tracing (4/10) • The weakness of SAT solvers • No timing concept. • Cannot detect  happened across time frames. • Can only distinguish the uncertainty but oscillations. • Notation • Time differential : T.

  25. Loop back tracing (5/10) nT-1 nT To represent the value of a node in T and T-1, we derive an equation with its fanins and trace back the fanin cone until the node be reached again as well as all variables in the equation are not in time T.

  26. Loop back tracing (6/10) SCC path 1 The output value of nT is not definite and violates combinationality. path 2 nT

  27. Loop back tracing (7/10) SCC SCC path 1 path 1 path 2 path 2 Condition: n should be 1 Time tag: T-1 nT nT Condition: n should be 0 Time tag: T-2

  28. Loop back tracing (8/10) SCC SCC path 1 SCC path 1 path 1 Condition: n should be 1 Time tag: T-1 Fin_cone Condition: n should be 0 Time tag: T path 2 path 2 nT nT nT

  29. Loop back tracing (9/10) SCC SCC SCC path 1 SCC path 1 path 1 path 1 Fin_cone path 2 path 2 nT nT nT nT path 2 Condition: signals never feedback Time tag: NO TAG

  30. Loop back tracing (10/10) SCC path 1 path 2 Condition: signals never feedback Time tag: NO TAG nkT = OSI1‧…‧OSIx‧ n1T-1‧…‧n1T-(feedback-2)‧n1T-(feedback-1)‧…‧n2T-(feedback-1)‧…‧ nkT-1‧nkT-2‧…‧nkT-(feedback) feedback: # of loops where node n involves itself. (feedback >= 2) nkT

  31. Program flow (1/1) Cyclic circuit C Find an SCC S Find a loop L in S SAT solving Derive the back tracing equation BTE of an ISIof L SAT SAT? UNSAT Transform BTE into the CNF YES Exists unfinished SCC? YES Exists unfinished ISI? NO NO YES Exists unfinished loop? termination NO

  32. Future work (1/1) Loops with inverters (debug). Equations reuse.

More Related