Ultralow-Power Design in Near-Threshold Region

1. Ultralow-Power Design inNear-Threshold Region Prof. : M. Shams Name: Yiqi Chang Student #:6624968

2. 5 6 1 2 3 4 7 Sense-Amplifier-Based PTL (SAPTL) Introduction Device and Circuit model Sensitivity Analysis Energy-Delay Optimization Architectural Optimization Conclusion Outline

3. Introduction Question: Why we need ultralow power? What is near-threshold region?

4. Introduction Optimization logic circuit Past five years minimum-energy point (MEP) Traditional minimum-delay operational point (MDP)

5. Introduction Fig. 1. pareto-optimal design curve Energy-delay trade-off in combinational logic.

6. Introduction Method to get ultralow power Use minimum-energy point Ultralow power design Voltage-based optimization Various architectural techniques

7. Device and Circuit model Current model: Current of starting point (VGS =VT) : n: subthreshold slope, μ: mobility , Cox: oxide capacitance, and thermal voltage ϕt =kT/q Current in the vicinity of VT: IC: inversion coefficient, and kfit is model-fitting parameter

8. Device and Circuit model inversion coefficient: the degree of inversion of the transistor sub-VT (IC<1)and above-VT (IC > 1)

9. Device and Circuit model Fig. 2 Inversion coefficient for HVT and LVT devices for a 65 nm technology.

10. Device and Circuit model Delay Model:

11. Device and Circuit model Energy Model:

12. Sensitivity Analysis gate sizing energy-delay trade-offs supply voltage threshold voltage

13. Sensitivity Analysis Sensitivity: a parameter x represents a percent reduction in energy for a percent increase in delay

14. Sensitivity Analysis

15. Sensitivity Analysis Formulas of S:

16. Sensitivity Analysis Good news for MEP region Easier to do than to adjust gate sizing. Not require any layout changes Could be done after chip fabrication

17. Energy-Delay Optimization 3 parameters for optimization: Supply Sizing VT(selected from the available discrete values)

18. Energy-Delay Optimization

19. Energy-Delay Optimization

20. Energy-Delay Optimization Make VT is variable for different regions of energy-delay cure

21. Sense-Amplifier-Based PTL (SAPTL) How to make VT various?

22. Sense-Amplifier-Based PTL (SAPTL) PTL no path from VDD to gnd

23. Sense-Amplifier-Based PTL (SAPTL) Dactive:sum of the sense amplifier and driver delays Dstack: the stack delay

24. Sense-Amplifier-Based PTL (SAPTL) www.themegallery.com

25. Architectural Optimization Some architectural can be used to get optimization Time-multiplexing technique www.themegallery.com

26. Architectural Optimization Pipelining for feedback time-multiplexed logic www.themegallery.com

27. Conclusion 1.MEP: expensive of performance. 2.MDP: expensive of energy. 3.Energy 20%↑ → 10-times in performance↑ 4.PTL outperforms standard CMOS in the near-threshold region(achieving lower energy). 5.The use of time-multiplexing: both lower area and energy without performance penalty (reduced leakage that comes with a lower area).

28. Thank You !