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CS 162 Discussion Section Week 5 10 / 7 – 10/ 11

CS 162 Discussion Section Week 5 10 / 7 – 10/ 11. Today’s Section. Project discussion (5 min) Quiz (5 min) Lecture Review ( 20 min) Worksheet and Discussion ( 20 min). Project 1. Autograder is still up submit proj1-test Due 10/8 ( Today! ) at 11:59 PM submit proj1-code

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CS 162 Discussion Section Week 5 10 / 7 – 10/ 11

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  1. CS 162 Discussion SectionWeek 510/7 – 10/11

  2. Today’s Section • Project discussion (5 min) • Quiz (5 min) • Lecture Review(20min) • Worksheet and Discussion (20 min)

  3. Project 1 • Autograder is stillup submit proj1-test • Due 10/8 (Today!) at 11:59 PM submit proj1-code • Due 10/9 (Tomorrow!) at 11:59 PM Final design doc & Project 1 Group Evals Template posted on Piazza last week Will post Group Evals Link on Piazza Wed Afternoon • Questions?

  4. Quiz…

  5. Short Answer • [Use this one] • Name the 4 types of cache misses discussed in class, given their causes: [0.5 each] • Program initialization, etc. (nothing you can do about them) [Compulsory Misses] • Two addresses map to the same cache line [Conflict Misses] • The cache size is too small [Capacity Misses] • External processor or I/O interference [Coherence Misses] • [Choose 1] • Which is better when a small number of items are modified frequently: write-back caching or write-through caching? [Write-back] • Name one of the two types of locality discussed in lecture that can benefit from some type of caching. [Temporal or Spatial] • True/False • [Choose 2] • Memory is typically allocated in finer grained units with segmentation than with paging. [False] • TLB lookups can be performed in parallel with data cache lookups [True] • The size of an inverted page table is proportional to the number of pages in virtual memory [False] • Conflict misses are possible in a 3-way-set-associative cache [True]

  6. Lecture Review

  7. Virtualizing Resources • Physical Reality: Processes/Threads share the same hardware • Need to multiplex CPU (CPU Scheduling) • Need to multiplex use of Memory (Today) • Why worry about memory multiplexing? • The complete working state of a process and/or kernel is defined by its data in memory (and registers) • Consequently, cannot just let different processes use the same memory • Probably don’t want different processes to even have access to each other’s memory (protection)

  8. Important Aspects of Memory Multiplexing • Controlled overlap: • Processes should not collide in physical memory • Conversely, would like the ability to share memory when desired (for communication) • Protection: • Prevent access to private memory of other processes • Different pages of memory can be given special behavior (Read Only, Invisible to user programs, etc) • Kernel data protected from User programs • Translation: • Ability to translate accesses from one address space (virtual) to a different one (physical) • When translation exists, process uses virtual addresses, physical memory uses physical addresses

  9. Untranslated read or write Virtual Addresses Physical Addresses CPU MMU Two Views of Memory • Address Space: • All the addresses and state a process can touch • Each process and kernel has different address space • Consequently, two views of memory: • View from the CPU (what program sees, virtual memory) • View from memory (physical memory) • Translation box (MMU) converts between the two views • Translation helps to implement protection • If task A cannot even gain access to task B’s data, no way for A to adversely affect B • With translation, every program can be linked/loaded into same region of user address space

  10. Address Segmentation Virtual memory view 1011 0000 + 11 0000 --------------- 1110 0000 Physical memory view 1111 1111 stack 1111 0000 (0xF0) stack 1110 0000 (0xE0) 1100 0000 (0xC0) heap 1000 0000 (0x80) heap 0111 0000 (0x70) data data 0101 0000 (0x50) 0100 0000 (0x40) code code 0001 0000 (0x10) 0000 0000 0000 0000 seg # offset

  11. Address Segmentation Virtual memory view Physical memory view 1111 1111 stack stack 1110 0000 1110 0000 1100 0000 What happens if stack grows to 1110 0000? heap 1000 0000 heap 0111 0000 data data 0101 0000 0100 0000 code code 0001 0000 0000 0000 0000 0000 seg # offset

  12. Address Segmentation Virtual memory view Physical memory view 1111 1111 stack stack 1110 0000 1110 0000 1100 0000 No room to grow!! Buffer overflow error or resize segment and move segments around to make room heap 1000 0000 heap 0111 0000 data data 0101 0000 0100 0000 code code 0001 0000 0000 0000 0000 0000 seg # offset

  13. Paging Page Table Virtual memory view Physical memory view 11111 11101 11110 11100 11101 null 11100 null 11011 null 11010 null 11001 null 11000 null 10111 null 10110 null 10101 null 10100 null 10011 null 10010 10000 10001 01111 10000 01110 01111 null 01110 null 01101 null 01100 null 01011 01101 01010 01100 01001 01011 01000 01010 00111 null 00110 null 00101 null 00100 null 00011 00101 00010 00100 00001 00011 00000 00010 1111 1111 1110 1111 stack 1111 0000 stack 1110 0000 1100 0000 heap 1000 0000 heap 0111 000 data data 0101 000 0100 0000 code code 0001 0000 0000 0000 0000 0000 page # offset

  14. Paging Page Table Virtual memory view Physical memory view 11111 11101 11110 11100 11101 null 11100 null 11011 null 11010 null 11001 null 11000 null 10111 null 10110 null 10101 null 10100 null 10011 null 10010 10000 10001 01111 10000 01110 01111 null 01110 null 01101 null 01100 null 01011 01101 01010 01100 01001 01011 01000 01010 00111 null 00110 null 00101 null 00100 null 00011 00101 00010 00100 00001 00011 00000 00010 1111 1111 stack stack 1110 0000 1110 0000 1100 0000 What happens if stack grows to 1110 0000? heap 1000 0000 heap 0111 000 data data 0101 000 0100 0000 code code 0001 0000 0000 0000 0000 0000 page # offset

  15. Paging Page Table Virtual memory view Physical memory view 11111 11101 11110 11100 11101 10111 11100 10110 11011 null 11010 null 11001 null 11000 null 10111 null 10110 null 10101 null 10100 null 10011 null 10010 10000 10001 01111 10000 01110 01111 null 01110 null 01101 null 01100 null 01011 01101 01010 01100 01001 01011 01000 01010 00111 null 00110 null 00101 null 00100 null 00011 00101 00010 00100 00001 00011 00000 00010 1111 1111 stack stack 1110 0000 1110 0000 1100 0000 stack Allocate new pages where room! heap 1000 0000 heap 0111 000 data Challenge: Table size equal to # of pages in virtual memory! data 0101 000 0100 0000 code code 0001 0000 0000 0000 0000 0000 page # offset

  16. Two-Level Paging Virtual memory view Page Tables (level 2) Physical memory view 111 110 null 101 null 100 011 null 010 001 null 000 1111 1111 stack 11 11101 10 11100 01 10111 00 10110 stack 1110 0000 1111 0000 Page Table (level 1) 1100 0000 stack 11 null 10 10000 01 01111 00 01110 heap 1000 0000 heap 0111 000 data 11 01101 10 01100 01 01011 00 01010 data 0101 000 0100 0000 11 00101 10 00100 01 00011 00 00010 code page2 # code 0001 0000 0000 0000 0000 0000 page1 # offset

  17. Two-Level Paging Virtual memory view Page Tables (level 2) Physical memory view 111 110 null 101 null 100 011 null 010 001 null 000 stack 11 11101 10 11100 01 10111 00 10110 stack 1110 0000 Page Table (level 1) stack 11 null 10 10000 01 01111 00 01110 1001 0000 (0x90) heap 1000 0000 (0x80) heap data 11 01101 10 01100 01 01011 00 01010 In best case, total size of page tables ≈ number of pages used by program virtual memory. Requires one additional memory access! data 11 00101 10 00100 01 00011 00 00010 code code 0001 0000 0000 0000

  18. Inverted Table Virtual memory view Physical memory view 1111 1111 stack stack 1110 0000 1110 0000 Inverted Table hash(virt. page #) = phys. page # 1100 0000 stack 1011 0000 h(11111) = h(11110) = h(11101) = h(11100) = h(10010)= h(10001)= h(10000)= h(01011)= h(01010)= h(01001)= h(01000)= h(00011)= h(00010)= h(00001)= h(00000)= 11101 11100 10111 10110 10000 01111 01110 01101 01100 01011 01010 00101 00100 00011 00010 heap 1000 0000 heap 0111 0000 data Total size of page table ≈ number of pages used by program in physical memory. Hash more complex data 0101 0000 0100 0000 code code 0001 0000 0000 0000 0000 0000 page # offset

  19. Address Translation Comparison

  20. Caching Concept • Cache: a repository for copies that can be accessed more quickly than the original • Make frequent case fast and infrequent case less dominant • Caching at different levels • Can cache: memory locations, address translations, pages, file blocks, file names, network routes, etc… • Only good if: • Frequent case frequent enough and • Infrequent case not too expensive • Important measure: Average Access time = (Hit Rate x Hit Time) + (Miss Rate x Miss Time)

  21. Probability of reference 0 2n - 1 Address Space Lower Level Memory Upper Level Memory To Processor Blk X From Processor Blk Y Why Does Caching Help? Locality! • Temporal Locality(Locality in Time): • Keep recently accessed data items closer to processor • Spatial Locality(Locality in Space): • Move contiguous blocks to the upper levels

  22. Sources of Cache Misses • Compulsory(cold start): first reference to a block • “Cold” fact of life: not a whole lot you can do about it • Note: When running “billions” of instruction, Compulsory Misses are insignificant • Capacity: • Cache cannot contain all blocks access by the program • Solution: increase cache size • Conflict(collision): • Multiple memory locations mapped to same cache location • Solutions: increase cache size, or increase associativity • Two others: • Coherence (Invalidation): other process (e.g., I/O) updates memory • Policy: Due to non-optimal replacement policy

  23. 32-Block Address Space: Block no. 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 Direct mapped: block 12 (01100) can go only into block 4 (12 mod 8) Set associative: block 12 can go anywhere in set 0 Fully associative: block 12 can go anywhere Block no. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Block no. Block no. Set 0 Set 1 Set 2 Set 3 Where does a Block Get Placed in a Cache? • Example: Block 12 placed in 8 block cache 01 100 01100 00 011 tag index tag index tag

  24. Which block should be replaced on a miss? • Easy for Direct Mapped: Only one possibility • Set Associative or Fully Associative: • Random • LRU (Least Recently Used) 2-way 4-way 8-waySize LRU Random LRU Random LRU Random 16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.0% 64 KB 1.9% 2.0% 1.5% 1.7% 1.4% 1.5% 256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12%

  25. What happens on a write? • Write through: The information is written both to the block in the cache and to the block in the lower-level memory • Write back: The information is written only to the block in the cache. • Modified cache block is written to main memory only when it is replaced • Question is block clean or dirty? • Pros and Cons of each? • WT: • PRO: read misses cannot result in writes • CON: processor held up on writes unless writes buffered • WB: • PRO: repeated writes not sent to DRAM processor not held up on writes • CON: More complex Read miss may require writeback of dirty data

  26. Virtual Address Physical Address Yes No Save Result Data Read or Write (untranslated) Caching Applied to Address Translation TLB Physical Memory CPU • Question is one of page locality: does it exist? • Instruction accesses spend a lot of time on the same page (since accesses sequential) • Stack accesses have definite locality of reference • Data accesses have less page locality, but still some… • Can we have a TLB hierarchy? • Sure: multiple levels at different sizes/speeds Cached? Translate (MMU)

  27. Virtual Page # tag / page # index Offset Overlapping TLB & Cache Access (1/2) • Main idea: • Offset in virtual address exactly covers the “cache index” and “byte select” • Thus can select the cached byte(s) in parallel to perform address translation virtual address physical address byte

  28. Putting Everything Together: Address Translation Physical Memory: Virtual Address: Virtual P1 index Virtual P2 index Offset PageTablePtr Physical Address: Physical Page # Offset Page Table (1st level) Page Table (2nd level)

  29. Putting Everything Together: TLB Physical Memory: Virtual Address: Virtual P1 index Virtual P2 index Offset PageTablePtr Physical Address: Physical Page # Offset Page Table (1st level) Page Table (2nd level) TLB: …

  30. Putting Everything Together: Cache Physical Memory: Virtual Address: Virtual P1 index Virtual P2 index Offset PageTablePtr Physical Address: Physical Page # Offset tag byte index Page Table (1st level) cache: tag: block: Page Table (2nd level) TLB: … …

  31. Worksheet…

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