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HVCMOS for CLICPix V2

HVCMOS for CLICPix V2. HVCMOS CCPD. …. NMOS. PMOS. LV. Plans. AMS H18 on high resistive substrate run ~November 2015 Substrate resistivities 20 Ohm – 1k Ω cm Depleted zone thicknesses: 15/30um (20/80 Ω cm), 50um (200 Ω cm), 100um (1k Ω cm)

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HVCMOS for CLICPix V2

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  1. HVCMOS for CLICPix V2

  2. HVCMOS CCPD • …. NMOS PMOS LV

  3. Plans • AMS H18 on high resistive substrate run ~November 2015 • Substrate resistivities 20 Ohm – 1k Ω cm • Depleted zone thicknesses: 15/30um (20/80Ω cm), 50um (200Ω cm), 100um (1kΩ cm) • Improvements – added source follower for better timing and less power constumption • Segmented pixels (16.6 um) • Run shared within ATLAS, Mu3e and CLIC • CLIC area ~ 5cm x 5cm • Cost ~ 160k for two substrate types • Intended power CLIC power per pixel ~1-2uW – peaking time 20ns (capacitance 20fF) 160-320mW • Pixel size 25 um x 25 um • Probably possible 16 um • Present scheme ~10uA for 200fF (50 x 250) – peaking time 20ns

  4. CLIC Pixel • CLIC Pixel • Size: 25um x 25um • Analog signal is transferred to CLICPIX readout chip, no discriminator in pixel • Simple and small pixels, small capacitance, smaller noise • Spatial resolution can be improved and time-walk can be corrected by measuring of signal amplitudes • Second stage amplifier added to increase output amplitude To CLICPIX BLR BL A OutAmp OutBL 2nd Stage

  5. Improvement • … BLRes BL A OutBL OutAmp VNFB 2nd Stage VNClic, VNLoad VNFoll RED: Bias Voltages generated internally BLUE: External Voltages

  6. Segmented pixel • … BLRes BL A OutBL Saturated signal OutAmp VNFB InR/L=En 2nd Stage VNClic, VNLoad Variable voltage VNFoll RED: Bias Voltages generated internally BLUE: External Voltages

  7. ATLAS pixel • Analog pixel • Size: 25um x 250um • Analog signal is transferred to the readout chip, no discriminator in pixel • Second stage amplifier added to increase the output amplitude • Simulated noise ~30e To FEI4 BLRes BL Middle pixels send two signal copies to two pads A OutBL OutAmp VNFB InR/L=En 2nd Stage VNClic, VNLoad Variable voltage VNFoll RED: Bias Voltages generated internally BLUE: External Voltages

  8. ATLAS Analog pixel: layout

  9. ATLAS pixel EnR row0(R),row1(L) InR(3:0) InL0 InL1 InL2 InL3 InR0 InR1 InR2 InR3 InL/R(0:3) EnL En(11:6) ampout L0 R0 L1 R1 L2 R2 Str Ld(0:2) dc ao InL(3:0) row2(R),row3(L) En(5:0) + + + + ampout En(5:0) SerOut Col(0:2) ao0 Col(3:5) ao1

  10. CCPDv4 Amplitude coding

  11. CLIC Pixel • Chip Layout 1.6mm

  12. CLIC Pixel • Simulation: Response to 1500 e input signal (MIP) • Signal amplitude: 370mV 370mV

  13. TSV

  14. Assembly Possibilities … Capacitive signal transmission Capacitive signal transmission Wire bonds for sensor chip Wire bond for sensor bias CMOS pixel sensor several reticles (e.g. 4 x 2 cm) CMOS pixel sensor several reticles (e.g. 4 x 2 cm) Pixel sensor (diode based) (e.g. 8 x 2cm) Wire bonds for RO chips Wire bonds for RO chips Wire bonds for RO chips Readout chip Readout chip TSVs Wire bonds for sensor chip Readout chip PCB CMOS pixel sensor with backside contacts CMOS pixel sensor Pixel sensor Backside contact Readout chips Readout chips PCB PCB PCB Detector as it is done now: Diode based pixel sensor bump-bonded to readout ASICs Present development: CMOS pixel sensor capacitively coupled to readout ASICs With TSVs CMOS pixel sensor with backside contacts capacitively coupled to readout ASICs

  15. Thank you!

  16. Chip-Top • CLIC pixels, size 25 x 25um • ATLAS Type A sub pixel size 33um x 125um • ATLAS Type B sub pixel size 25um x 125um 2x3-col 2x4-col 64 x 25um col 4 special columns (CLIC) A N CLIC Diode for laser tests Separated guard bias Bias Block mon Analog-multiplexer Mon-Amplifier AO

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