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On Chip Nonlinear Digital Compensation for RF Receiver

On Chip Nonlinear Digital Compensation for RF Receiver. Karen M. G. V. Gettings, Andrew K. Bolstad, Show-Yah Stuart Chen, Benjamin A. Miller and Michael Vai HPEC 2011.

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On Chip Nonlinear Digital Compensation for RF Receiver

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  1. On Chip Nonlinear Digital Compensation for RF Receiver Karen M. G. V. Gettings, Andrew K. Bolstad, Show-Yah Stuart Chen, Benjamin A. Miller and Michael Vai HPEC 2011 This work is sponsored by the Department of the Air Force under Air Force contract FA8721-05-C-0002. Opinions, interpretations, conclusions and recommendations are those of the author and are not necessarily endorsed by the United States Government.

  2. System On Chip Equalization System-on-chip • We designed a nonlinear digital compensation circuitry that is part of a System On Chip (SOC) design • SOC implementations are an attractive solution for SWaP restricted applications, partly because of targeted design needs • We exploit the benefits of SOC implementations by co-designing the analog hardware and digital processing I Nonlinear Digital Equalizer ADC IP core Homodyne receiver with anti-alias filter Q Frequency Synthesizer Previous Work: NLEQ Processor +20~25 dB SFDR/IFDR @500MHz BW >1 Teraops < 2 Watts Before Equalization After Equalization In-Band Intermodulation Distortions Dynamic range improvement Power (dB) Power (dB) Frequency (bin) Frequency (bin) Song et al., “Nonlinear Equalization Processor IC for Wideband Receivers and Sensors,” HPEC 2009

  3. Nonlinear Digital Equalizer Design • Established a low-power standard-cell synthesis design flow • IBM 65 nm CMOS process • Created an overall compensation architecture customized for our current front end system • Design is optimized to minimize power consumption Analog Input Delay S PE1 shifter Offset Binary to Two’s Complement Conversion x(n) Final Accumulator x2(n) PE2 shifter x3(n) PE3 shifter x4(n) PE4 shifter PE5 shifter

  4. Projected Design Performance • The digital compensation architecture has been synthesized, placed, routed and taped-out • Core size: 200 mm by 200 mm • Simulation results show: • Approximately 10 mW of power at 200 MHz • Compensation of front end filter: • 15 dB improvement for median dynamic range 200 mm 15 dB

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