Howd - Zur Hung Eric Lai Wei Jie Lee Yu - Chiang Lee Design Manager: Jonathan P. Lee

1. [M2] Huffman Encoder Project Howd - Zur Hung Eric Lai Wei Jie Lee Yu - Chiang Lee Design Manager: Jonathan P. Lee Overall Project Objective:Design a Low Power Huffman Encoder Presentation #3 February 7th, 2007

2. Huffman Encoder Project Status Design ProposalChip ArchitectureBehavioral Verilog Implementation Size estimates/floorplanning Behavioral Verilog simulated Gate Level DesignComponent Layout/SimulationChip LayoutComplete Simulation

3. Huffman Encoder Project About … Implement Huffman compression portion of GZIP on a single chip Provide fast & energy efficient compression for network devices

4. Huffman Encoder Project What is GZIP? • Based on the DEFLATE algorithm, which is a combination of LZ77 and Huffman coding • Widely used in the HTTP/1.1 protocol and general purpose data compression • GZIP software compression speed(100 Mbits per second)

5. Huffman Encoder Project Currently in Market: AHA362-PCIX 3.0 Gbits/sec GZIP Compression/Decompression Accelerator PCI-X, 64-bit, 133 MHz edge card interface Ideal for SAN servers, virtual tape emulation backup and recovery systems Huge, power hungry, require built-in processor

6. Huffman Encoder Project Our Target Market Network Server, on chip solution for network card and motherboard Portable Devices

7. Huffman Encoder Project Design Constraints Clock Speed >= 133MHz Hard to get benchmark for size and power in the market Optimize for power once speed constraint is met

8. Huffman Encoder Project Detailed Block Diagram from Week 2

9. Huffman Encoder Project Design Decision (week 3) • Add MemSelect module • Add TraverseAddr module • Serial Output

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14. Huffman Encoder Project Serial Output

15. Huffman Encoder Project MemSelectFrequencyGroup

16. Huffman Encoder Project MemSelectLengthCode

17. Huffman Encoder Project Transistor Count (week 2) SRAM (Freq / Group) ~ 4,000 SRAM (Code / Length) ~ 7,000Adders ~ 1,000Comparators ~ 1,000FSM Control Logic ~ 1,000Registers ~ 1,000 Buffer ~ 2,000 Others (mux, demux, etc.) ~ 4,000 Total ~21,000

18. Huffman Encoder Project Updated Transistor Count SRAM (Freq / Group) ~ 4,000 SRAM (Code / Length) ~ 7,000CountFrequency ~ 650 Find2Least ~ 2,500 Combine ~ 1,530 TraverseAddr ~ 440 SerialOutput ~ 1,300 MemSelect ~ 1,370 FSM Control ~ 500 Total ~19,290

19. Huffman Encoder Project Initial Floorplan Find2Least Code/Length SRAM TraverseAddr Traverse Addr MemSelectFrequency/Group Combine Frequency/Group SRAM FSM Control SerialOutput MemSelectLength/Code CountFrequency

20. Huffman Encoder Project Behavioral Verilog `include "SRAM_freqGroup.v" `include "countFreq.v" `include "control.v" module top(input clk, reset, en, start, done, input [4:0] dataIn, output ERR); wire [20:0] freqGroup, freqGroup1, freqGroup2; wire [3:0] enPhase, resetPhase; control control1(clk, reset, start, done, findReady, combineReady, oneGroupLeft, finish, enPhase, resetPhase); SRAM_freqGroup SRAM_freqGroup1(re, we, clk, reset, dataIn, freqGroup); countFreq countFreq1(clk, reset, start, freqGroup[20:5], freqGroup[4:0], re, we, ERR); find2Freq find2Freq1(freqGroup1, freqGroup2, freqGroupIn, ready, clk, reset, en); endmodule module topT(output reg clk, reset, en, start, done, output reg [4:0] dataIn, input ERR); always #10 clk = ~clk; initial begin $monitor($time,, "clk=%b, reset=%b, dataIn=%b, ERR=%b", clk, reset, dataIn, ERR); clk = 0; reset = 0; done = 0; en = 0; #20; reset = 1; #20; reset = 0; start = 1; dataIn = 5'b01101; #10; en = 1; // enPhase[0] should be on at time = 50 #10; dataIn = 5'b01111; #40; dataIn = 5'b01101; #40; dataIn = 5'b11001; #80; dataIn = 5'b01111; #80; $finish; end endmodule

21. Huffman Encoder Project Behavioral Verilog Simulation Waveform

22. Huffman Encoder Project Problems Timing Issues Multiple Clocks???