FPGA based Software Defined Radio

1. University of Rennes 1 – IRISA/ InriaENSSAT – 6 rue de kerampont – 22300 Lannion France http://www.irisa.fr/cairn IRISA / Inria – Cairn Team Energy-Efficient Reconfigurable Computing Architectures An FPGA Software Defined Radio Platform with a High-Level Synthesis Design Flow VaibhavBhatnagar, Ganda StephaneOuedraogo, Matthieu Gautier, Arnaud Carer and Olivier Sentieys IRISA, INRIA, University of Rennes, France Abstract Software defined radio (SDR) opens a new doorto future Internet of Thingswithhigherdegree of designingflexibilityin context of wireless system development. Prototypinga remoteimplementation of wirelessprotocols on a hardware over the web requires a highly versatile software radio platformalongwith laid-back designingtools. To thisaim, an FPGA-based SDR scheme has been proposedcombiningVirtex-6 Perseus 6010 platformcapabilities and a design flow based on High-LevelSynthesis(HLS) tools. A full IEEE 802.15.4 (ZigBee) physical layer has been implementedon the proposedplatformfrom a C-languagedataflowspecification. All the results have been analyzed to lead to a faircomparisonbetweendifferent design flows. Although the proposed SDR has somedesigning issues, it shows a noticeabledesigningpotentialityto flexible prototyping of future wirelesssystems. FPGA based Software Defined Radio New methodology: fromhighlevelspecifications to FPGA integration • FPGA design fromhighlevelspecifications • Key issues : • specificdevelopmentmethodologyallowing the flexibilityof high-levelspecifications, • a modularplatformsupportingvariouswaveforms. • In thispaper: • NutaqPerseusplatformexperience • Integrationwithhigh-levelsynthesis design • DSL: SynchronousData Flow withcontroller • Block-levelspecificationusinglibrary (C++/VHDL blocks) • IntegrationusingVivado (ISE) design suite SDR platformintegrationflows IEEE 802.1.4 experience feedback • Wecompare: • TwoVHDL design flows: • HLS flow from C-languagespecification (CatapultC) • Hand-coded VHDL design • Perseus 6010 developmenttools: • MBDK: Matlab Simulink GUI tool • BSDK: Script basedtool IEEE 802.15.4 transceiver Integrationresults of IEEE 802.15.4 on Perseus 6010 platform Receivedbasebandsignals in Chip-scope Transmittedbasebandsignals in Chip-scope Workingtest benchPerseus HLS-VHDL Modulatedspectrum The Nutaqplatform • NutaqPerseus 6010 board • Virtex-6 FPGA • Developmenttools • Mezzanine add-oncards • Nutaq Radio420X FPGA mezzanine card • SISO full duplex RF transceiver • Wide frequency range: 300 MHz - 3 GHz • Selectablebandwidth: 1.5 - 28 MHz • 12 bits and 40 MBPS (DAC and ADC) Resource estimation of IEEE 802.15.4 transmitterdesigns Centre de Recherche INRIA – Rennes Bretagne Atlantique

2. SDR high-level specifications Algorithm Waveform description language Multi-rate framer Design constraints Domain-specificlanguage C/C++ IP 1 IP 2 IP N IP N-1 Hand-coded VHDL High Level Synthesis VHDL design Library .tcl .tcl .tcl .tcl IP loading HLS tools IP loading HLS tools IP_x.cpp HLS tools IP_x_v1.vhd N Waveformdesign IP_x_v2.vhd .vhd .vhd .vhd .vhd IP_x_v3.vhd .cpp Framer design .vhd Third-party blocks RTL merging Sriptbasedtools Graphical User Interface tools .vhd FPGA integration .vhd Bitstreamgeneration Platform integration .bit Bit stream To FPGA To FPGA