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EENG 2710 Chapter 4. Modular Combinational Logic. Chapter 4 Homework. EENG 2710 Xilinx Project 1 And EENG 2710 VHDL Project 2 (Projects are on Instructor’s Website). Basic Decoder. Decoder: A digital circuit designed to detect the presence of a particular digital state.

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eeng 2710 chapter 4

EENG 2710 Chapter 4

Modular Combinational Logic

chapter 4 homework

Chapter 4 Homework

EENG 2710 Xilinx Project 1

And

EENG 2710 VHDL Project 2

(Projects are on Instructor’s Website)

basic decoder
Basic Decoder
  • Decoder: A digital circuit designed to detect the presence of a particular digital state.
  • Can have one output or multiple outputs.
  • Example: 2-Input NAND Gate detects the presence of ‘11’ on the inputs to generate a ‘0’ output.
single gate decoders
Single-Gate Decoders
  • Uses single gates (AND/NAND) and some Inverters.
  • Example: 4-Input AND detects ‘1111’ on the inputs to generate a ‘1’ output.
  • Inputs are labeled D3, D2, D1, and D0, with D3 the MSB (most significant bit) and D0 the LSB (least significant bit).
single gate decoders1
Single-Gate Decoders

D3

D3

D2

D2

D1

D1

D0

D0

Y = (D3

D2

D1

D0)’

Y = D3

D2

D1

D0

single gate examples
Single-Gate Examples
  • If the inputs to a 4-Input NAND are given as

, then the NAND detects the code 0001. The output is a 0 when the code 0001 is detected.

  • This type of decoder is used in Address Decoding for a PC System Board.
multiple output decoders
Multiple Output Decoders
  • Decoder circuit with n inputs can activate m = 2n load circuits.
  • Called a n-line-to-m-line decoder, such as a 2-to-4 or a 3-to-8 decoder.
  • Usually has an active low enable that enables the decoder outputs.
simulation
Simulation
  • Simulation: The verification of a digital design using a timing diagram before programming the design in a Complex Programmable Logic Device (CPLD).
  • Used to check the Output Response of a design to an Input Stimulus using a timing diagram.
vhdl binary decoder
VHDL Binary Decoder
  • Use select signal assignment statements constructs or conditional signal assignment statements constructs.
2 to 4 decoder vhdl entity
2-to-4 Decoder VHDL Entity
  • Using a select signal assignment statement:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY decode3a IS

PORT(

d : IN STD_LOGIC_VECTOR (1 downto 0);

g : IN STD_LOGIC

y : OUT STD_LOGIC_VECTOR (3 downto 0));

END decode3;

selected signal entity
Selected Signal Entity
  • In the previous slide, the Entity used a STD LOGIC Array for Inputs and Outputs.
  • The Y : OUT STD_LOGIC_VECTOR(3 downto 0) is equal to Y3, Y2, Y1, Y0.
  • The STD_LOGIC Data Type is similar to BIT but has added state values such as Z, X, H, and L instead of just 0 and 1.
selected signal assignments
Selected Signal Assignments
  • Uses a VHDL Architecture construct called WITH SELECT.
  • Format is:
    • WITH (signal input(s)) SELECT.
    • Signal input states are used to define the output state changes.
2 to 4 decoder vhdl architecture
ARCHITECTURE decoder OF decode2to4 IS

SIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0);

BEGIN

inputs(2) <= g;

inputs (1 downto 0) <= d;

WITH inputs SELECT

y <= "0001" WHEN "000",

"0010" WHEN "001",

"0100" WHEN "010",

"1000" WHEN "011",

"0000" WHEN others;

END decoder;

2-to-4 Decoder VHDL Architecture

d(1)

g

d(0)

Default case

Y(3)

Y(0)

2 to 4 decoder vhdl architecture1
2-to-4 Decoder VHDL Architecture

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY decode3a IS

PORT(

d : IN STD_LOGIC_VECTOR (1 downto 0);

g : IN STD_LOGIC

y : OUT STD_LOGIC_VECTOR (3 downto 0));

END decode3;

ARCHITECTURE decoder OF decode2to4 IS

SIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0);

BEGIN

inputs(2) <= g;

inputs (1 downto 0) <= d;

WITH inputs SELECT

y <= "0001" WHEN "000",

"0010" WHEN "001",

"0100" WHEN "010",

"1000" WHEN "011",

"0000" WHEN others;

END decoder;

decoder architecture
Decoder Architecture
  • The decoder Architecture used a SELECT to evaluate d to determine the Output y.
  • Both d and y are defined as an Array (or bus or vector) Data Type.
  • The last state for WHEN OTHERS is added for the other logic states (Z, X, H, L, etc.).
seven segment displays
Seven-Segment Displays
  • Seven-Segment Display: An array of seven independently controlled LEDs shaped like an 8 that can be used to display decimal digits.
common anode display
Common Anode Display
  • Common Anode Display (CA): A seven- segment display where the anodes of all the LEDs are connected together to VCC and a ‘0’ turns on a segment (a to g).
common cathode display
Common Cathode Display
  • Common Cathode Display (CC): A seven-segment display where all the cathodes are connected and tied to ground, and a ‘1’ turns on a segment.
seven segment decoder driver
Seven-Segment Decoder/Driver
  • Receives a BCD (Binary Coded Decimal) 4-Bit input, outputs a BCD digit 0000 – 1001 (0 through 9).
  • Generates Outputs (a–g) for each of the display LEDs.
  • Requires a current limit series resistor for each segment.
seven segment decoder driver1
Seven-Segment Decoder/Driver
  • Decoders for a CC-SS have active high outputs while decoders for a CA-SS have active low outputs (a to g).
  • The outputs generated for the binary input combinations of 1010 to 1111 are “don’t cares”.
  • The decoder can be designed with VHDL Logic (7447, 7448).
decoder driver entity ca
Decoder/Driver Entity (CA)

ENTITY bcd_7seg IS

PORT(

d3, d2, d1, d0 : IN BIT;

a, b, c, d, e, f, g : OUT BIT;

END bcd_7seg;

decoder driver architecture
ARCHITECTURE seven_segment OF bcd_7seg IS

SIGNAL input : BIT_VECTOR (3 downto 0);

SIGNAL output : BIT_VECTOR (6 downto 0);

BEGIN

input <= d3 & d2 & d1 & d0;

-- Uses two intermediate signals called input and output (internal no pins)

-- Creates an array by using the concatenate operator (&)

In this case input(3) <= d3, input(2) <= d2, etc.

Decoder/Driver Architecture
decoder driver architecture1
WITH input SELECT

output <= “0000001” WHEN “0000”,

“1001111” WHEN “0001”,

“0010010” WHEN “0010”,

“0000110“ WHEN “0011”,

• • •

• • •

• • •

“1111111” WHEN others;

Decoder/Driver Architecture
decoder driver architecture2
a <= output(6);

b <= output(5);

c <= output(4);

d <= output(3);

e <= output(2);

f <= output(1);

g <= output(0);

END seven_segment

Decoder/Driver Architecture
ss vhdl file description
SS VHDL File Description
  • In the preceding example file, a concurrent select signal assignment was used (WITH (signals) SELECT.
  • The intermediate output signals were mapped to the segments (a to g).
  • Example: when Input (D3 – D0) is 0001, the decoder sets a=d=e=f=g=1, b=c=0.
encoders
Encoders
  • Encoder: A digital circuit that generates a specific code at its outputs in response to one or more active inputs.
  • It is complementary in function to a decoder.
  • Output codes are usually Binary or BCD.
priority encoders
Priority Encoders
  • Priority Encoder: An encoder that generates a code based on the highest- priority input.
  • For example, if input D3 = input D5, then the output is 101, not 011. D5 has a higher priority than D3 and the output will respond accordingly.
bcd priority encoder
BCD Priority Encoder

D9 – D0 = 0100001111

BCD # = ?

bcd priority encoder1
BCD Priority Encoder

D9 – D0 = 0101001011

Q3 – Q0 = 1000 (810)

bcd priority encoder2
BCD Priority Encoder

D9 – D0 = 1000000001

Q3 – Q0 = 1001 (910)

bcd priority encoder3
BCD Priority Encoder

D9 – D0 = 1101001011

Q3 – Q0 = 1001 (910)

put it all together
Put It All Together

D

= 1

C

= 0

B

= 0

A

= 0

1

priority encoder vhdl entity
-- hi_pri8a.vhd

ENTITY hi_pri8a IS

PORT(

d : IN BIT_VECTOR (7 downto 0);

q : OUT BIT_VECTOR (2 downto 0));

END hi_pri8a;

Priority Encoder VHDL Entity
priority encoder vhdl architecture
ARCHITECTURE a OF hi_pri8a IS

BEGIN

-- Concurrent Signal Assignments

q(2) <= d(7) or d(6) or d(5) or d(4);

q(1) <= d(7) or d(6)

or ((not d(5)) and (not d(4)) and d(3))

or ((not d(5)) and (not d(4)) and d(2));

q(0) <= -- in a similar fashion

END a;

Priority Encoder VHDL Architecture
basic multiplexers mux
Basic Multiplexers (MUX)
  • (MUX): A digital circuit that directs one of several inputs to a single output based on the state of several select inputs.
  • A MUX is called a m-to-1 MUX.
  • A MUX with n select inputs will require m = 2n data inputs (e.g., a 4-to-1 MUX requires 2 select inputs S1 and S0).
multiplexer logic
Multiplexer Logic
  • Boolean expression for a 4-to-1 MUX is
  • This expression can be expanded to any size MUX so the VHDL architecture could use a very long concurrent Boolean statement.
double subscript notation
Double Subscript Notation
  • Naming convention in which variables are bundled in numerically related groups, the elements of which are themselves numbered.
  • The first subscript identifies the group that a variable belongs to (D01, D00).
  • The second subscript indicates which element of the group a variable represents.
vhdl constructs for muxs
VHDL Constructs For MUXs
  • The following three VHDL constructs can be used to describe the Multiplexer:
    • Concurrent Signal Assignment Statement
    • Select Signal Assignment Statement
    • CASE Statement
process and sensitivity list
PROCESS and Sensitivity List

PROCESS: A VHDL construct that contains statements that are executed if a signal in its sensitivity list changes.

Sensitivity list: A list of signals in a PROCESS statement that are monitored to determine whether the Process should be executed.

case statement
Case Statement
  • A case statement is a VHDL construct in which there is a choice of statements to be executed, depending on the value of a signal or variable.
case vhdl template
CASE __expression IS

WHEN __constant_value =>

__statement;

__statement;

WHEN __constant_value =>

__statement;

__statement;

WHEN OTHERS =>

__statement;

__statement;

END CASE;

Case VHDL Template
mux 4 to 1 vhdl 1
Basic Entity declaration for a 4-to-1 MUX:

ENTITY mux4case IS

PORT(

d0, d1, d2, d3 : IN BIT;

s : IN BIT_VECTOR (1 downto 0);

y : OUT BIT);

END mux4case;

MUX 4-to-1 VHDL – 1
mux 4 to 1 vhdl 2
ARCHITECTURE mux4to1 OF mux4case IS

BEGIN

-- Monitor select inputs and execute if they change

PROCESS(s)

BEGIN

CASE s IS

MUX 4-to-1 VHDL – 2
mux 4 to 1 vhdl 3
WHEN "00" => y <= d0;

WHEN "01" => y <= d1;

WHEN "10" => y <= d2;

WHEN "11" => y <= d3;

WHEN others => y <= \'0\';

END CASE;

END PROCESS;

END mux4to1;

MUX 4-to-1 VHDL – 3
multiplexer applications
Multiplexer Applications
  • Used in directing multiple data sources to a single processing element such as multiple CD Player Streams to a DSP.
  • Used in Time Division Multiplexing (TDM) by the Phone Service to multiplex multiple voice channels on a single coax line (or fiber).
multiplexer applications1

Multiplexer Applications

Used in directing multiple data sources to a single processing element such as multiple CD Player Streams to a DSP.

multiplexer applications2

Multiplexer Applications

Used in Time Division Multiplexing (TDM) by the Phone Service to multiplex multiple voice channels on a single coax line (or fiber).

time division multiplexing tdm
Time Division Multiplexing (TDM)
  • Each user has a specific time slot in a TDM data frame. Each frame has 24 users.
  • TDM requires a time-dependent (counter) source to synchronize the select lines.
  • Each user’s time slot repeats on the next frame for more data.
  • The links are called T-Carriers (such as a T1 Line).
tdm data streams
TDM Data Streams
  • Two methods in which data is transmitted:
    • Bit Multiplexing: One bit is sent at a time from the channel during the channel’s assigned time slot
    • Word Multiplexing: One byte is sent at a time from the channel during the channel’s assigned time slot
demultiplexer basics
Demultiplexer Basics
  • Demultiplexer: A digital circuit that uses a decoder to direct a single input (from a MUX) to one of several outputs.
  • A DEMUX performs the reverse operation of a MUX.
  • The selected output is chosen by the Select Inputs (as in a MUX).
demultiplexer basics1
Demultiplexer Basics
  • Designated as a 1-to-n DEMUX that requires m select inputs such that n outputs = 2m select inputs.
  • 1-to-4 DEMUX Equations:
  • They are similar to a MUX and can be designed using CASE Statements.
demultiplexer vhdl entity
ENTITY dmux8 IS

PORT(

s : IN STD_LOGIC_VECTOR (2 downto 0);

d : IN STD_LOGIC;

y : OUT STD_LOGIC_VECTOR (0 to 7));

END dmux8;

Demultiplexer VHDL Entity
demultiplexer vhdl architecture
ARCHITECTURE a OF dmux8 IS

SIGNAL inputs : STD_LOGIC_VECTOR (3 downto 0);

BEGIN

inputs <= d & s;

WITH inputs select

Y <= “01111111” WHEN “0000”,

“10111111” WHEN “0001”,

• • •

• • •

“11111111” WHEN others;

END a;

Demultiplexer VHDL Architecture
analog mux demux
Analog MUX/DEMUX
  • Uses a CMOS Switch or Transmission Gate that will allow a signal to Pass in two directions for + and – Voltages.
  • Some commercial types such as a CD4066 or 74HC4066.
  • Multiplexes 4 CMOS Switches to a single output (Y) for analog multiplexing.
magnitude comparators
Magnitude Comparators
  • Magnitude Comparator: A digital circuit that compares two n-Bit Binary Numbers and indicates if they are equal or which is greater.
  • A very simple One-Bit Magnitude Comparator is the Two-Input XNOR Gate:
    • When both inputs are equal, the output is a 1; if they are not, it is a 0.
2 bit comparator
2-Bit Comparator

A1

B1

AEQB

A0

B0

2 bit magnitude comparator
2-Bit Magnitude Comparator

A1

B1

AEQB

A0

B0

AGTB

ALTB

magnitude comparators1
Magnitude Comparators
  • Multiple Bit Comparisons
  • Also adds A > B (AGTB) and A < B (ALTB) Outputs.
  • For A > B, start with the MSB:
    • If An–1 > Bn–1, then AGTB = 1
  • If not, then try the next most significant bit.
4 bit magnitude comparator
4-Bit Magnitude Comparator

A3

B3

ALTB

A2

B2

AEQB

A1

B1

A0

AGTB

B0

vhdl 4 bit magnitude comparator
ENTITY compare4 IS

PORT(

a, b : IN INTEGER RANGE 0 to 15;

agtb, aeqb, altb : OUT STD_LOGIC);

END compare4;

VHDL 4-Bit Magnitude Comparator
vhdl 4 bit magnitude comparator1
ARCHITECTURE a OF compare4 IS

SIGNAL compare :STD_LOGIC_VECTOR (2 downto 0);

BEGIN

PROCESS (a, b)

BEGIN

IF a<b THEN

compare <= “110”;

ELSIF a = b THEN

compare <= “101”;

VHDL 4-Bit Magnitude Comparator
vhdl 4 bit magnitude comparator2
VHDL 4-Bit Magnitude Comparator

ELSIF a > b THEN

compare <= “011”;

ELSE

compare <= “111”;

END IF;

agtb <= compare(2);

aeqb <= compare(1);

altb <= compare(0);

END PROCESS

END a;

parity basics
Parity Basics
  • Parity: A digital system that checks for errors in a n-Bit Binary Number or Code.
  • Even Parity: A parity system that requires the binary number and the parity bit to have an even # of 1s.
  • Odd Parity: A parity system that requires the binary number and the parity bit to have an Odd # of 1s.
parity basics1
Parity Basics
  • Parity Bit: A bit appended on the end of a binary number or code to make the # of 1s odd or even depending on the type of parity in the system.
  • Parity is used in transmitting and receiving data by devices in a PC called UARTs, that are on the COM Port.
  • UART = Universal asynchronous

Receiver/Transmitter

parity calculation
Parity Calculation
  • N1 = 0110110:
    • It has four 1s (an even number).
    • If Parity is ODD, the Parity Bit = 1 to make it an odd number (5).
    • If Parity is EVEN, the Parity Bit = 0 to keep it an even number (4).
  • N2 = 1000000:
    • One 1 in the data.
    • Podd = 0.
    • Peven = 1.
parity generation hw
Parity Generation HW
  • A basic two-bit parity generator can be constructed from a XOR Gate.
  • When the two inputs are 01 or 10, the output is a 1 (so this is even parity).
  • When the two inputs are 00 or 11, the output is a 0.
  • For a parity generator of n bits, add more gates.
parity generator hw
Parity Generator HW
  • Cascading a long chain of XOR gates could cause excessive propagation delays.
  • To check for a Parity error, the receiver (RX) just generates a new Parity Bit (P1) based on the received parallel data and then compares it to the parity bit transmitted (P2).
parity generator hw1
Parity Generator HW
  • If there is an error, the two bits (P1 and P2) will not be equal, and we can use a two-bit magnitude comparator to check this (an XOR gate).
  • This check is called syndrome.
    • If there are no errors, the syndrome output (Perr) is 0.
  • Parity is not a foolproof system.
    • If two bits are in error, the error is not detected.
vhdl generate statement
__generate_label:

FOR __index_variable IN __range GENERATE

__statement;

__statement;

END GENERATE;

VHDL GENERATE Statement
4 bit parity vhdl code
LIBRARY ieee;

USE ieee.std_logic1164.ALL;

ENTITY parity4_gen IS

PORT(

d : IN STD_LOGIC_VECTOR (0 to 3);

pe ; OUT STD_LOGIC);

END parity4_gen;

4-Bit Parity VHDL Code
4 bit parity vhdl code1
ARCHITECTURE parity OF parity4_gen IS

SIGNAL p : STD_LOGIC_VECTOR (1 to 3);

BEGIN

p(1) <= d(0) xor d(1);

parity_generate:

FOR i IN 2 to 3 GENERATE

p(i) <= p(i-1) xor d(i);

END GENERATE;

pe <= p(3);

END parity;

4-Bit Parity VHDL Code
binary adders
Binary Adders
  • Half Adder (HA): A circuit that will add two bits and produce a sum bit and a carry bit.
  • Full Adder (FA): A circuit that will add a carry bit from another HA or FA and two operand bits to produce a sum bit and a carry bit.
basic ha addition
Basic HA Addition
  • Binary Two-Bit Addition Rules:

0 + 0 = 00

0 + 1 = 01

1 + 1 = 10

ha circuit
HA Circuit
  • Basic Equations: S = A XOR B, C = A and B where S = Sum and C = Carry.
  • Truth Table for HA Block:
full adder basics
Full Adder Basics
  • Adds a CIN input to the HA block.
  • Equations are modified as follows:
  • A FA can be made from two HA blocks and an OR Gate.
parallel adders
Parallel Adders
  • A circuit, consisting of n full adders, that will add n-bit binary numbers.
  • The output consists of n sum bits and a carry bit.
  • COUT of one full adder is connected to CIN of the next full adder.
ripple carry
Ripple Carry
  • In the n-Bit Parallel Adder (FA Stages) the Carryout is generated by the last stage (FAN).
  • This is called a Ripple Carry Adder because the final carryout (Last Stage) is based on a ripple through each stage by CIN at the LSB Stage.
ripple carry1
Ripple Carry
  • Each Stage will have a propagation delay on the CIN to COUT of one AND Gate and one OR Gate.
  • A 4-Bit Ripple Carry Adder will then have a propagation delay on the final COUT of 4  2 = 8 Gates.
  • A 32-Bit adder such as in an MPU in a PC could have a delay of 64 Gates.
look ahead carry
Look-Ahead Carry
  • Fast Carry or Look-Ahead Carry:
    • A combinational network that generates the final COUT directly from the operand bits (A1 to An, B1 to Bn).
    • It is independent of the operations of each FA Stage (as the ripple carry is).
look ahead carry1
Look Ahead Carry
  • Fast Carry has a small propagation delay compared to the ripple carry.
  • The fast carry delay is 3 Gates for a 4-Bit Adder compared to 8 for the Ripple Carry.
subtractor 2 s complement
Subtractor (2’s Complement)
  • The concept of Subtraction using 2’s Complement addition allows a Parallel FA to be used.
  • The subtract operation involves adding the inverse of the subtrahend to the minuend and then adding a 1.
subtractor 2 s complement1
Subtractor (2’s Complement)
  • This operation can be done in a parallel n-Bit FA by inverting (B1 to Bn) and connecting CIN at the LSB Stage to +5 V.
  • The circuit can be modified to allow either the ADD or SUBTRACT operation to be performed.
parallel binary adder subtractor
Parallel Binary Adder/Subtractor
  • XOR gates are used as programmable inverters to pass binary numbers (e.g., B1B2B3B4) to the parallel adder in true or complemented form.
overflow
Overflow
  • If the sign bits of both operands are the same and the sign bit of the sum is different from the operand sign bits, an overflow has occurred.
  • Overflow is not possible if the sign bits of the operands are different from each other.
overflow examples
Overflow Examples
  • Adding two 8-bit negative numbers:
  • Adding two 8-bit positive numbers:
bcd adder
BCD Adder
  • A Parallel Adder whose output sum is in groups of 4 bits, each representing a BCD (8421) Digit.
  • Basic design is a 4-Bit Binary Parallel Adder to generate a 4-Bit Sum of A + B.
  • Sum is input to the four-bit input of a Binary-to-BCD Code Converter.
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