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ELEC1700 Computer Engineering 1 Week 10 Monday lecture Memory Semester 1, 2013 PowerPoint PPT Presentation


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ELEC1700 Computer Engineering 1 Week 10 Monday lecture Memory Semester 1, 2013. Memory basics ROM RAM Memory expansion. Memory. Basic memory array. 000. Smallest unit of storage is a bit Most applications store data in bytes (8 bits) or multiples of bytes

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ELEC1700 Computer Engineering 1 Week 10 Monday lecture Memory Semester 1, 2013

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Elec1700 computer engineering 1 week 10 monday lecture memory semester 1 2013

ELEC1700Computer Engineering 1Week 10

Monday lectureMemory

Semester 1, 2013


Elec1700 computer engineering 1 week 10 monday lecture memory semester 1 2013

Memory basics

ROM

RAM

Memory expansion

Memory


Basic memory array

Basic memory array

000

  • Smallest unit of storage is a bit

  • Most applications store data in bytes (8 bits)

    • or multiples of bytes

  • Location of a unit of data in a memory is called the address

  • Capacity of a memory is the total number of data units stored

001

010

011

100

101

110

111

Example:

  • 8 addresses

    000,001,…,111

  • 64-bit capacity


Write operation

Write operation

Address register

Data register

Address decoder

Byte organized memory array

Address bus

Data bus

Write

  • address is placed on the address bus

  • data placed on data bus

  • a WRITE command is issued

  • Contents of data register overwrites original memory contents


Read operation

Read operation

Address register

Data register

Address decoder

Byte organized memory array

Address bus

Data bus

Read

  • address is placed on the address bus

  • a READ command is issued

  • memory puts a copy of the data on the data bus, content of which is read into the data register

  • The read operation is actually a “copy” operation

    • original data is not changed

  • The data bus is a “two-way” path — bidirectional


Ram and rom

RAM and ROM

Two major categories of semiconductor memory:

  • RAM = random-access memory

    • “random access” – all addresses can be selected in any order

    • also called read/write memory

    • volatile: stores data only when power is applied

  • ROM = read-only memory

    • Data storage is permanent (or semi-permanent)

    • Non-volatile: Retains stored data when power turned off

    • Example: BIOS (basic input-output system)


Elec1700 computer engineering 1 week 10 monday lecture memory semester 1 2013

Memory basics

ROM

RAM

Memory expansion

Memory


Rom family

ROM family


256 4 rom

256 × 4 ROM

Address

Memory locations

Hex Binary

00

00000000

01

00000001

02

00000010

:

:

:

:

:

:

:

FF

11111111

A total of 256×4 bits stored

1 kbit ROM (1k = 210 = 1024)

4 bits


Internal rom organisation

Internal ROM organisation


Rom access time

ROM access time

  • To read from ROM:

    • ROM enabled with chip select pin /CS

    • address placed on address bus

    • data appears on data bus (after a delay)

  • ROM access time is measured from address change to data available


Proms eproms and eeproms

PROMs, EPROMs and EEPROMs

VPP

A0

A1

O0

A2

O1

A3

O2

A4

O3

A5

O4

A6

O5

A7

O6

A8

O7

A9

A10

CE/PGM

OE

  • PROM = programmable ROM

    • fused link is burned open during the programming process. Programming cannot be reversed

  • EPROM = erasable PROM

    • erased by exposure to UV light through a window. To program it, a high voltage is applied to VPP and OE is brought LOW

  • EEPROM = electrically erasable PROM


Elec1700 computer engineering 1 week 10 monday lecture memory semester 1 2013

Memory basics

ROM

RAM

Memory expansion

Memory


Ram family

RAM family

SRAM

Bits stored in a latch or flip-flop

DRAM

Bits stored as charge on a capacitor


Basic sram array

Basic SRAM array

  • SRAM memory cell based on a D latch

  • Dout = Din while Select is HIGH

  • Dout latched when Select goes LOW


Tri state outputs

Tri-state outputs

Week10Mon_tristate.circ


Bidirectional buses

Bidirectional buses


Organisation of sram

Organisation of SRAM


32k 8 sram

32k × 8 SRAM

  • 215 address lines

  • 215 = 25 × 210 = 32 × 1k = 32k

  • 8 I/O lines, so 32k × 8

  • Chip select /CS

    All inputs ignored unless asserted

  • Write enable /WE

    /WE and /CS asserted enables input buffers

    • data bus → RAM

  • Output enable /OE

    /OE and /CS asserted enables output buffers

    • RAM → data bus


Sram timing

SRAM timing

  • Read cycle sequence

  • A valid address is put on the address bus

  • Chip select is LOW

  • Output enable is LOW

  • Data placed on data bus by SRAM

  • Write cycle sequence

  • A valid address is put on the address bus

  • Chip select is LOW

  • Write enable is LOW

  • Data is placed on the data bus by microprocessor


Dynamic ram dram

Dynamic RAM (DRAM)

  • DRAMs store data bits as a charge on a capacitor

  • Advantage: very simple

    • Large memories at low cost per bit

  • Disadvantage: storage capacitor loses charge

    • Needs refreshing every 8–16 ms

    • Refresh circuitry built into DRAM chips

Capacitors covered in detail in ELEC1300

“The difference between SRAM and DRAM is that SRAM works and DRAM doesn't”


Dram organisation

DRAM organisation

Refresh circuitry

  • DRAMs use address multiplexing to reduce number of address lines

  • Example: 1M × 1 DRAM

    • 220 addresses since

      220 ~1,000,000 = 1M

    • But only 10 address lines

    • A0 time-shares with A10

      A1 shares with A11, etc.

/RAS = row address strobe

/CAS = column address strobe


Cache memory

  • L2 cache

  • Fast but expensive, so limited size

  • ~2MB

  • Cheap and “slow”

  • ~4GB

  • L1 cache in processor

  • Fast but very limited storage

  • ~32kB

Cache memory

Cache analogy:

  • Home refrigerator ~ cache

  • Supermarket ~ main memory


Elec1700 computer engineering 1 week 10 monday lecture memory semester 1 2013

Memory basics

ROM

RAM

Memory expansion

Memory


Memory modules

Memory modules

  • DRAM chips commonly supplied on circuit boards

  • SIMMs = single in-line memory modules

    • 32-bit data

    • Capacities up to 64 MB

  • DIMMs = dual in-line memory modules

    • 64-bit data

    • Capacities 1GB and more


Word length expansion

Word-length expansion

Expansion of two 65,536 x 4 ROMs into a 65,536 x 8 ROM


Word capacity expansion

Word-capacity expansion

Two 1M x 8 RAMs configured as a 2M x 8 RAM


Word capacity expansion1

Word-capacity expansion

What are the ranges of addresses in RAM 1 and RAM 2?


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