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vhdl to place-and-route design flow tutorial

7/31/2001. WLT. Major Changes in This Revision. Added explanation for Display Options and Find forms.Added section on

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vhdl to place-and-route design flow tutorial

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    1. 7/31/2001 WLT VHDL to Place-and-Route Design Flow Tutorial By: Wei Lii Tan Advisor: Dr. Robert Reese This revision: October 30, 2001

    2. 7/31/2001 WLT

    3. 7/31/2001 WLT Introduction This tutorial will guide you through the synthesis of a fully placed-and-routed design from a VHDL entity. The tutorial will use the following CAD tools: - Synopsys Design Compiler - Cadence Design Planner - Cadence Silicon Ensemble - Cadence ICFB - Modelsim QHDL

    4. 7/31/2001 WLT Introduction The following conventions will be used in this tutorial: - File names will be in italics, e.g. /ccs/issl/micro/users/tan/myfile.vhd - User input (e.g. what you need to type) will be in boldface, e.g. type swsetup cadence-ncsu

    5. 7/31/2001 WLT The Example Design The design we will be using as an example for this tutorial is a VHDL model of a Dallas Semiconductor DS1620k temperature sensing kit. The interface reads the temperature from the DS1620k, then outputs the data to a seven-segment digit display. The design also includes some simple gates for debugging, such as a NAND gate, NOR gate, inverter, and a DFF. A simple counter is included in the design too.

    6. 7/31/2001 WLT The Example Design The main top-level signals in the design are: inv_in, inv_out: input and output for simple inverter nand2in_a, nand2in_b, nand2_out: inputs and output for simple NAND gate. nor2in_a, nor2in_b, nor2_out: inputs and output for simple NOR gate. _csb_6_ to _csb_0_: Signals for MSB of the seven-segment digit display. _lsb_6_ to _lsb_0_: Signals for LSB of the seven-segment digit display.

    7. 7/31/2001 WLT Copying Example Files Copy the entire directory /ccs/issl/micro/users/tan/tutorials/design_flow into your work directory *important*All directories will start with your_work_directory/design_flow, unless specified otherwise.

    8. 7/31/2001 WLT Design Flow

    9. 7/31/2001 WLT Synopsys Design Compiler This tool will convert a VHDL model to a Verilog model. It requires the use of the following user-provided files: - Library file, in .db format. - Script file (file extension .script) - The VHDL file to be converted to Verilog. At this stage, we will be using Design Compiler to generate a Verilog model, without pads, of a VHDL file called topchip_gold_nopads.

    10. 7/31/2001 WLT Synopsys Design Compiler The VHDL file that we will be using is topchip_nopads.vhd. Using a script file with Design Compiler, we will convert this VHDL model to verilog. The next page shows the script file used to compile topchip_nopads.vhd. The script file is called topchip_nopads.script

    11. 7/31/2001 WLT Synopsys Design Compiler Script File link_library=target_library={jennings_pads_noqn.db} define_design_lib tempsense -path /ccs/issl/micro/users/tan/dallas1/sc_tests/myfiles/vhdl2/rtl/tempsense analyze -work tempsense -f vhdl { ../rtl/tempsense/topchip_final_components.vhd ../rtl/tempsense/bin2bcd_mod.vhd ../rtl/tempsense/pulse.vhd ../rtl/tempsense/twoscomp.vhd ../rtl/tempsense/sev_seg_display.vhd ../rtl/tempsense/ds1620_i.vhd ../rtl/tempsense/simple_gate.vhd ../rtl/tempsense/topchip_count4.vhd} read -f vhdl ../rtl/tempsense/topchip_gold_nopads.vhd set_flatten true max_area 0.0 current_design topchip_gold_nopads compile -ungroup_all -map_effort medium dont_touch_network CLK dont_touch_network clk dont_touch_network find(pin, */r) set_max_fanout 8.0 find(design, topchip_gold_nopads) compile -incremental_mapping -map_effort medium check_design verilogout_single_bit = true write -f verilog -output ../gate/topchip_gold_nopads_noqn.v quit

    12. 7/31/2001 WLT Why use a script file? Using a script file with dc_shell is equivalent to typing the exact commands in dc_shell interactively. A script file automates the process of typing in all the commands manually.

    13. 7/31/2001 WLT What is the .db file for? The database (.db) file holds information about the standard cell library used to implement the VHDL design. It provides information about the standard cells: the names of the standard cells, input/output ports, as well as timing characteristics and functionality.

    14. 7/31/2001 WLT Design Compiler Change to the directory synopsys/run_syn Type swsetup synopsys Type dc_shell –f topchip_nopads.script The ‘-f’ option tells design compiler to use a script file, and not run in interactive mode. 5. After design compiler finishes (it should take about 5 minutes to finish the compilation), a verilog netlist file called topchip_nopads.v should be created in the directory synopsis/gate.

    15. 7/31/2001 WLT Design Compiler Note: If a verilog netlist file with the same name exists in the target directory, design compiler will overwrite it. Now that we have a verilog file, our next step would be to simulate the verilog netlist to check for errors.

    16. 7/31/2001 WLT Modelsim The next step in the design flow is simulating the verilog netlist that was generated using Synopsys Design Compiler. Change to the qhsim directory, and type swsetup modelsim. If the qhsim/work directory does not exist, create one by typing qhlib work. - The ‘qhlib work’ command creates a directory called ‘work’, and also stores Modelsim information in the ‘work’ directory. This directory will be the object directory for standard cells and top-level designs that are compiled using Modelsim.

    17. 7/31/2001 WLT Modelsim Before we compile our top-level design (topchip_nopads.v), we need to compile the standard cells that make up topchip_nopads.v. In the qhsim directory, type: qvlcom ../synopsys/gate/libcells.v. 4. Type: qvlcom ../synopsys/gate/topchip_nopads.v. This will compile our top-level design file. 5. Now, type: qvlcom ../synopsys/gate/tb_topchip_nopads.v. This will compile the testbench for our design. The testbench supplies input vectors needed to test the functionality of our design.

    18. 7/31/2001 WLT Modelsim To enter Qhsim and simulate our design, type: qhsim tb_topchip_nopads. Note that the argument after the ‘qhsim’ command refers to the Verilog module name of our design, not the file name. After you do step 6, you should see a screen that looks like Figure 1. In the command window, type view signals <enter> and view wave <enter>. These commands bring up the signals and waves windows respectively.

    19. 7/31/2001 WLT Figure 1: Modelsim Command Window

    20. 7/31/2001 WLT Modelsim 8. Go to the signals window, click on view -> wave -> signals in region. This will add all the top-level signals to the wave window. 9. Type run 150 us in the command window. This will run the testbench for 150 microseconds. 10. Note that all the commands that you entered in the command window can be entered into a text file, then recalled by typing do filename in the command window.

    21. 7/31/2001 WLT Figure 2: Simulation Results Waveform

    22. 7/31/2001 WLT Getting Ready to Import into Design Planner Now that we have verified that the Verilog netlist works properly, let’s import the Verilog netlist into Cadence Design Planner. Cadence’s family of CAD tools have stricter rules about naming ports and nets, compared to Modelsim. Therefore, we need to get rid of some unwanted symbols in our Verilog netlist. Symbols like front-slashes, back-slashes, and other numerical operators are not allowed in net names, if you are using Cadence tools.

    23. 7/31/2001 WLT Getting Ready to Import into Design Planner Copy the file topchip_nopads.v from the synopsys/gate directory to the cadence/dp_se/netlist directory. Change to the cadence/dp_se/netlist directory. Run the perl script called synopsys/gate/myfilter.pl on the verilog netlist file, by typing: perl ../../../synopsys/gate/myfilter.pl topchip_nopads.v 4. This will filter out all the unwanted characters from the netlist file.

    24. 7/31/2001 WLT Starting Design Planner Change to the directory cadence/dp_se. From this directory, the main subdirectories are: run: This will be the directory to invoke all of the Design Planner tools. tech: Contains the tech.dpux file. netlist: contains the gate level verilog netlist

    25. 7/31/2001 WLT Starting Design Planner (continued from previous page) design_db_ami06: Contains the pillar database of the design jennings_ami06_pads_noqn: Contains the pillar database of the standard cells.

    26. 7/31/2001 WLT Starting Design Planner 3. Change to the run directory. 4. Type “swsetup cadence-dp” 5. Type “areaPdp –tech ../tech &”. This will invoke the Design Planner. You should see two windows: the Pillar window, and the AreaPdp PCW log window.

    27. 7/31/2001 WLT Importing the Netlist 1. In the Pillar window, click on: File -> Import -> Verilog 2. Wait for the ver2hld form to show up - it may take a couple of minutes to show up, and clicking on other menu items at this time may cause the program to crash.

    28. 7/31/2001 WLT Importing the Netlist 3. In the ver2hld form, type in “../netlist/topchip_nopads.v” for input verilog filename. 4. Check the run translation box, and type “topchip_nopads” for name of top cell. 5. Check the name of global nets box, and type “vdd” for power, “gnd” for ground.

    29. 7/31/2001 WLT Importing the Verilog Netlist into Design Planner 6. In the ver2hld form, check the tie nets (up down) box, and enter “vdd gnd” for that field. 7. Type in “design_db_ami06” for the output library name. Make sure the ‘Create Pins for Top Layer of Cell’ box is checked, and Metal1 is the selected layer for the pins. Click on OK. This will generate an AutoLayout view for topchip_nopads.v.

    30. 7/31/2001 WLT Figure 3: Ver2hld form

    31. 7/31/2001 WLT Floorplanning (Design Planner) 1. In the Pillar window, click on File -> Explore Libraries 2. In the Library Browse form, double click on design_db_ami06, topchip_nopads, then autoLayout. 3. The areaPdp main edit window will show up. Notice that all blocks and cells are placed at the origin (0,0).

    32. 7/31/2001 WLT Figure 4: topchip_nopads autoLayout, before Floorplan Initialization

    33. 7/31/2001 WLT Initializing the Floorplan (Design Planner) 1. In the areaPdp edit window, click on Floorplan -> Initialize 2. The Initialize Floorplan form will appear. Estimate aspect ratio will determine the aspect ratio of the design – any value other than 1.0 will generate a rectangular design, while 1.0 will generate a square design.

    34. 7/31/2001 WLT Initializing the Floorplan (Design Planner) 3. Enter 100 for I/O Circuit to Core Dist 4. Make sure that the Move-Fixed box is checked, and the None box is not checked. 5. Click the Apply & Close button.

    35. 7/31/2001 WLT Figure 5: After Floorplan Initialization

    36. 7/31/2001 WLT Placing Pins (Design Planner) 1. In the areaPdp window, click on Place -> I/O -> Pads/Pins 2. A form will appear. Select the following selections for the form fields: I/O Init Module: Print Random Io File I/O Init Filename: ioPlace I/O Init File Format: normal

    37. 7/31/2001 WLT Placing Pins (Design Planner) I/O Init I/O Boundary Mode: Generate new I/O Init I/O Side Ordering: B:R->L R:T->B T:L->R L:B->T 3. Click on the Apply button. This will generate a file called ioPlace that contains I/O cell placement information.

    38. 7/31/2001 WLT Placing Pins (Design Planner) 4. Now that the ioPlace file has been generated, we will proceed to actually place the I/O pads with the information contained in the ioPlace file. 5. Change I/O Init Module to Load File & Auto Place 6. Change I/O Init I/O Boundary Mode to Maintain Existing

    39. 7/31/2001 WLT Placing Pins (Design Planner) 7. Click on the Apply & Close button. 8. In the areaPdp edit window, you should see the top layer pins placed evenly on all four sides of the boundary. 9. Save your design as ‘pins’ by clicking on File -> Save as… , then typing ‘pins’ for the save filename.

    40. 7/31/2001 WLT Figure 6: Place I/O Form

    41. 7/31/2001 WLT Figure 7: After Pin Placement

    42. 7/31/2001 WLT Creating Supply Rings (Design Planner) 1. In the areaPdp window, click on Floorplan -> Preroutes -> Supply Rings 2. The create supply rings form will appear. 3. Click on Nets: Named. Type “vdd gnd” for the names. 4. Select Area for ring mode. Check Snap to grid.

    43. 7/31/2001 WLT Creating Supply Rings (Design Planner) 5. Now we will enter the characteristics for the horizontal and vertical ring layers. For LayerH, select met1, type in “4.5 4.5” for width(s) and “3 3” for spacing(s). 6. For LayerV, select met2, type in “4.5 4.5” for width(s) and “3 3” for spacing(s). 7. This will create supply rings for vdd and gnd 4.5 units wide, with 3 units spacing in between, using metal 1 for the horizontal ring portions and metal 2 for the vertical ring portions.

    44. 7/31/2001 WLT Figure 8: Route Rings Form

    45. 7/31/2001 WLT Creating Supply Rings (Design Planner) 8. Click on the Apply & Close button. 9. The mouse cursor will change into a crosshair. Click on the top left corner of the ring, then the bottom right corner. The positions you click will be used as the inner positions of the supply ring, so be sure to leave some space outwards of the positions you click on. You should now be able to see the supply rings in the areaPdp window.

    46. 7/31/2001 WLT Creating Supply Rings (Design Planner) Save your file as ‘supply_rings’. Note: If you are using an xterm connection to run Design Planner (i.e. you are not using a UNIX machine), Design Planner will have a tendency to freeze when saving files. Unfortunately you cannot do anything about this, except to save often, so that if Design Planner happens to freeze while you are saving a file, you can always go back to your last saved version. Sometimes it helps to make sure the library browse window is closed before saving files.

    47. 7/31/2001 WLT Figure 9: After Creating Supply Rings

    48. 7/31/2001 WLT Creating Region of Rows (Design Planner) In the areaPdp window, click on Floorplan -> Rows -> Create region of rows 2. Set Site Name as core. 3. Set Row orientation as Horizontal. 4. Uncheck the Number of rows box. 5. Check Channel Offset, and set offset to 0.0 6. Check Site Orient Pattern and set Orient to R0. 7. Set Pattern to R0 MX (type-in field) 8. Check the Abutted box.

    49. 7/31/2001 WLT Figure 10: Draw Site Region Form

    50. 7/31/2001 WLT Creating Region of Rows (Design Planner) Click the Apply button. The mouse cursor should change into a crosshair. Click the top left corner of the region to be created, then click the bottom right corner. The region should be placed somewhere inside the pad frame, within the supply rings. 11. A region of rows is created; this is where the single height logic cells will be placed.

    51. 7/31/2001 WLT Creating Region of Rows (Design Planner) Now, change Site Name to dbl_core. 13. Repeat the process for the dbl_core rows. Try to get the dbl_core and core rows to overlap as closely as possible – design planner will automatically ‘snap’ them into place. 14. This will create a region of rows for double-height cell placement. 15. Save your design as ‘rows’.

    52. 7/31/2001 WLT Creating Region of Rows (Design Planner) Note about creating rows: Try to have both the core and dbl_core regions overlap each other exactly. If they don’t, Design Planner might crash when you are placing the cells. You can zoom into an area (right-click and drag) or out of an area (left-click the zoom out button on the right of the editing window), even while you are placing the rows. You can also pan left, right, up or down when placing the rows. Click on the arrow buttons to the right of the editing window.

    53. 7/31/2001 WLT Creating Region of Rows (Design Planner) You should first zoom in to the top-left corner of the region of rows when your cursor looks like a crosshair. Then left click once on the top-left corner of the region of rows. Zoom out so you can see the entire region, the zoom into the bottom right corner. Left click again on the bottom right corner of the region of rows. This should allow you to place overlapping regions easily.

    54. 7/31/2001 WLT Figure 11: After Creating Region of Rows

    55. 7/31/2001 WLT Qplace (Design Planner) The next step is to use Qplace to automatically place standard cells within the pad frame, inside the region of rows we created earlier. 1. In the areaPdp window, click on Place -> Blocks/Cells (Qplace) 2. Leave the settings as the defaults, then click on Apply and Close.

    56. 7/31/2001 WLT Figure 12: Qplace Sequencer Form

    57. 7/31/2001 WLT Qplace (Design Planner) This process may take a few minutes. After that, the standard cell blocks should be placed inside the region of rows. If the region of rows you created earlier was too small for the cells to fit, an error message will be generated and Qplace will fail. After Qplace succeeds, save your design as ‘qplaced’.

    58. 7/31/2001 WLT Figure 13: After QPlace

    59. 7/31/2001 WLT Exporting to DEF Format (Design Planner) 1. In the areaPdp window, click on Interfaces -> Silicon Ensemble -> Export -> DEF 2. In the hld2def form, specify an output filename for the DEF file. This should go into the Output Def File Name slot. Include the desired path for the target file too.

    60. 7/31/2001 WLT Exporting to DEF Format (Design Planner) 3. Type “../def_files/topchip_nopads_qplaced.def” for the Output Def File Name. 4. Set the DEFOUT Library Name to design_db_ami06. 5. Type in “topchip_nopads” for DEFOUT Cell Name. 6. Type in ‘qplaced’ for the DEFOUT View Name. DEFOUT will use this saved file to generate the Def file.

    61. 7/31/2001 WLT Exporting to DEF Format (Design Planner) Fill in the rest of the options according to Figure 14, on next slide (be sure that the technology, floorplan, pins sections are clicked under “DEFOUT sections”) 8. Click on OK. 9. This will generate the Def file: cadence/dp_se/def_files/topchip_nopads_qplaced.def

    62. 7/31/2001 WLT Figure 14: DEF File Output Form

    63. 7/31/2001 WLT Why export to DEF? The DEF format is Cadence’s method of transporting designs from one Cadence CAD tool to another. DEF stands for ‘Design Exchange Format’. You will need to export to DEF when transferring a design from Design Planner to Silicon Ensemble, or from Silicon Ensemble to ICFB.

    64. 7/31/2001 WLT Silicon Ensemble We will now move on to using Silicon Ensemble to complete the design flow. 1. Quit AreaPdp by closing the Pillars window. 2. Make sure that you are in the cadence/dp_se/run directory. 3. In the terminal window, type: swsetup cadence-se sedsm & This will start Silicon Ensemble.

    65. 7/31/2001 WLT Importing the LEF File (Silicon Ensemble) 1. In Silicon Ensemble, click on File -> Import -> LEF. 2. In the Import LEF form, select the file ../tech/jennings_ami06_pads_noqn.lef, then click on OK.

    66. 7/31/2001 WLT Importing the LEF File (Silicon Ensemble) 3. In the Silicon Ensemble window, click on File -> Import -> DEF. 4. In the Import DEF window, Select the file ../def_files/topchip_nopads_qplaced.def 5. Click on OK. 6. If the design does not show up, click on Fit in the Silicon Ensemble window to view the design.

    67. 7/31/2001 WLT Figure 15: The Imported DEF File

    68. 7/31/2001 WLT Viewing Layers (Silicon Ensemble) To view nets, special wires, pins, cell boundaries etc. while you are working on your design, make sure all the appropriate Vs (visible) fields are checked.

    69. 7/31/2001 WLT Adding Filler Cells (Silicon Ensemble) 1. Click on Place -> Filler Cells -> Add Cells. 2. In the SROUTE Add Filler Cells form, type in “FILL” for Model, and “fill” for prefix. 3. Make sure ONLY the North and Flip South boxes are checked. 4. In the special pins section, add one entry for vdd and one entry for gnd (refer to Figure 16 on the next slide)

    70. 7/31/2001 WLT Figure 16:Add Filler Cells Form

    71. 7/31/2001 WLT Adding Filler Cells (Silicon Ensemble) 5. Click on OK. 6. This will add filler cells to your design. Filler cells provide n-well continuity for your standard cells.

    72. 7/31/2001 WLT Figure 17: After Adding Filler Cells

    73. 7/31/2001 WLT Routing Power (Silicon Ensemble) 1. Click on Route -> Route Power -> Follow Pins. 2. In the Layers section of the Sroute Follow Pins form, set Width to 1.80. 3. Click on OK.

    74. 7/31/2001 WLT Figure 18: Sroute Follow Pins Form

    75. 7/31/2001 WLT Figure 19: After SRoute Follow Pins

    76. 7/31/2001 WLT Wroute (Silicon Ensemble) 1. Click on Route -> Wroute. 2. In the Wroute form, click on OK. Wroute will run. This will take a few minutes to complete. After this point, all the interconnect routing of the design has been done.

    77. 7/31/2001 WLT Figure 20: After WRoute

    78. 7/31/2001 WLT Viewing Different Layers in Silicon Ensemble You won’t be able to see the interconnect metal layers in Figure 20 unless you enable the layer to be viewable. Click on View -> Layers. In the Layer Visibility form, click on All Objects, then check all the layer check boxes.

    79. 7/31/2001 WLT Display Options Silicon Ensemble allows you to customize the view window to display/not display certain parts of your design. In the main window, click on View -> Display Options…

    80. 7/31/2001 WLT Display Options Notice the top part of the Display Option form allows you to select ‘On, Here, Big, Small etc’ for the Level. By choosing a level here and clicking on the checkboxes, the selection for that particular checkbox will rotate between ‘OFF’ and the level you chose. For example, select Small for the level. Now, click once on the Cells checkbox in the Objects section. If the checkbox was originally set to On, it will switch to Off after the first time you click it. Click on it again to set it to Small. Click on Apply.

    81. 7/31/2001 WLT Display Options Your cell boundaries will now only be visible when you are zooming into a smaller portion of the design. If you click on the Fit button in the main window, you will not see the cell boundaries any more. Try zooming into a small area of the design. The cell boundaries will be visible again.

    82. 7/31/2001 WLT Display Options The following explains the different levels: - On: visible at any level. - Here: visible at level that is currently displayed in the main window. - Big, medium, small: visible at big, medium or small levels respectively. - Off: not visible at any level.

    83. 7/31/2001 WLT Checking Pin Names You can easily check to see the names of the routed pins in the standard cells using the Display Options form. In the Names section of the Display Options form, set Pins to On, or Small. Click on the Apply button. The pin names will now be visible.

    84. 7/31/2001 WLT The Find Form You can find cells, nets and pins etc. with the Find form. Click on Edit -> Find… to access the Find form. On the Find form, set Type to Net. Type msb_dp for the Name. Set the background dimmer to 70, then click on the Hilight button. The display will be dimmed, while the msb_dp net will be highlighted in the color selected in the Find form.

    85. 7/31/2001 WLT

    86. 7/31/2001 WLT The Find Form You can also give partial names, e.g. msb* instead of msb_dp. If you click on the Show List checkbox, you will see a list of matching names. Type _csb* for the net name, click on Show Lists, then click on Find. You should see a list of net names starting with ‘_csb’.

    87. 7/31/2001 WLT The Find Form You can now click on each individual entry in the list, and highlight the particular net, or select it. The Find form, together with the Display Options form, provide a convenient way of debugging your overall routed design.

    88. 7/31/2001 WLT Checking for Violations Violations will appear as ‘X’ marks on your design. Be sure that there are no violations created during the routing. Silicon Ensemble will tell you the number of violations created during Wroute (Refer to Figure 21, on the next slide). If there are any violations, be sure to fix them before moving on. You should not get any violations for this exercise.

    89. 7/31/2001 WLT Figure 21: Total Number of Violations Reported by Silicon Ensemble

    90. 7/31/2001 WLT Export to DEF Format (Silicon Ensemble) 1. Click on File -> Export -> DEF. 2. Type “../def_files/topchip_nopads_wrouted.def” for the DEF file name. 3. Make sure the All checkbox is checked. 4. Click on OK. This will create the DEF file cadence/dp_se/def_files/topchip_nopads_wrouted.def.

    91. 7/31/2001 WLT Running SEDSM in Script Mode When using SEDSM in interactive mode (like we just did), SEDSM will echo back your commands in the command-line window. If you enter these commands into a text file, you can run SEDSM in script mode. To run SEDSM in script mode, type the following in the cadence/dp_se/run directory: sedsm –b –gd=ansi “EXECUTE script.mac;” & where script.mac is the name of your script file.

    92. 7/31/2001 WLT Running SEDSM in Script Mode The cadence/dp_se/run directory has a script file called topchip_nopads.mac which will essentially perform all the procedures we did in interactive mode, from importing the LEF file to exporting the topchip_nopads_wrouted.def file. To execute the script file, go the the cadence/dp_se/run directory, and type: sedsm –b –gd=ansi “EXECUTE topchip_nopads.mac;” &

    93. 7/31/2001 WLT Re-running SEDSM after a Crash If Silicon Ensemble crashes while you are running it, you need to delete all the .dtp files in the cadence/dp_se/run directory before you run it again. The .dtp files are the lock files for Silicon Ensemble

    94. 7/31/2001 WLT Cadence ICFB Cadence ICFB is the last CAD tool in this design flow. In ICFB, our design can be exported into a HSpice netlist, a Verilog netlist, or GDSII / CIF formats, among others. Cadence ICFB is potentially the most powerful CAD tool among the tools in this design flow, but it is also the most complex.

    95. 7/31/2001 WLT Starting ICFB If you’ve previously used Design Planner or Silicon Ensemble in your current xterm window, launch a new xterm window. Change to the cadence/dfII directory. Type swsetup cadence-ncsu. Type “icfb &” to launch ICFB. You should see three windows pop up: the ICFB Command Interpreter Window (CIW), the Library Manager window, and another windows telling you about the changes for the latest version of ICFB. Close the third window.

    96. 7/31/2001 WLT Importing DEF into ICFB In the CIW, click on File -> Import -> DEF. Enter “tutorial” for Library Name, “topchip_nopads” for Cell Name, and “autoRouted” for View Name. Enter “../dp_se/def_files/topchip_nopads_wrouted.def” for DEF File Name. Make sure Silicon Ensemble is checked. Refer to Figure 22 (next slide) for all other options in the form. Click on ‘OK’. You will see some warning messages (about not being able to find site Core and site Double core). Ignore these messages.

    97. 7/31/2001 WLT Figure 22: Import DEF Form

    98. 7/31/2001 WLT Figure 23: topchip_nopads autoRouted view

    99. 7/31/2001 WLT Importing DEF into ICFB Open the autoRouted view of topchip_nopads. In the autoRouted view, before you do anything, click on Design -> Save. This ensures that if anything goes wrong, you can always come back to the autoRouted view. Click on Tools -> Layout. This changes the tool from abstract-editing mode to layout-editing mode.

    100. 7/31/2001 WLT Importing DEF into ICFB Click on Edit -> Search… In the Search form, search for inst in current cellview, with view name = abstract. Replace with view name -> layout. (Refer to Figure 24, next slide, click on ‘add criteria’ then choose “view name” criteria) Click on Apply, then Replace All. Close the search form, then click on Design -> Save as… Save the design in the same library and cell, but change the view to ‘layout’. When you close the editing window, you will be asked if you want to save changes for the autoRouted view. Do not save any changes here or the autoRouted view will be over-written.

    101. 7/31/2001 WLT Figure 24: Search Form

    102. 7/31/2001 WLT Viewing Layers in ICFB Whenever in ICFB’s layout editor, you can press shift-f to increase the number of layers viewed, or ctrl-f to decrease the number of layers viewed. For example, if you press shift-f while viewing the topchip_nopads layout, you will be able to see the metal, poly, active etc. layers of the individual standard cells. If you press ctrl-f, you will only be able to see the boundaries of the individual standard cells.

    103. 7/31/2001 WLT Figure 25: topchip_nopads layout view

    104. 7/31/2001 WLT Extracting a Verilog Netlist We need to extract a Verilog netlist out of our placed-and-routed design to verify that the place-and-route tools did their jobs without errors. This Verilog netlist will be simulated using Modelsim to verify for correct functionality.

    105. 7/31/2001 WLT Extracting a Verilog Netlist Before starting this section, change to the directory /ccs/issl/micro/users/tan/tutorials/design_flow/cadence/dfII. Then, type: rm –rf topchip_nopads.verilog This will clear the Verilog netlister work directory.

    106. 7/31/2001 WLT Extracting a Verilog Netlist First, we need to create an extracted view of our design. Open the layout view of topchip_nopads. Change the editing tool to layout editing by clicking on Tools -> Layout. Click on Verify -> Extract… Make sure the macro cell box is checked. (Refer Figure 26, next slide) Click on OK. The extraction process will take a few minutes to complete.

    107. 7/31/2001 WLT Figure 26: The Extractor Form

    108. 7/31/2001 WLT Extracting a Verilog Netlist Click on Tools -> Verilog-XL. You should see a new form called Setup Environment pop up on your screen. Enter “topchip_nopads.verilog” for the simulation run directory. Simulate the design in: Library: tutorial Cell: topchip_nopads View: extracted 10. Click on OK. (sample form is on next slide)

    109. 7/31/2001 WLT Figure 27: Setup Environment Form

    110. 7/31/2001 WLT Extracting a Verilog Netlist You will see a warning message as shown below. Ignore this warning message, since we are not going to simulate our design using Cadence. We are only going to use ICFB to extract a Verilog netlist.

    111. 7/31/2001 WLT Extracting a Verilog Netlist The Verilog-XL Integration window will now pop up. Click on Setup -> Netlist… The Verilog Netlisting Options form will pop up. Click on the More >> button. This will enable you to see all the options for this form. For the Netlist These Views field, enter: “behavioral functional symbol verilog”. For the Stop Netlisting at Views field, enter: “behavioral functional symbol”. Enter “vdd” and “gnd” for Global Power Nets and Global Ground Nets, respectively. Make sure the netlist explicitly box is checked. Then, Click on OK.

    112. 7/31/2001 WLT Figure 28: Verilog Netlisting Options Form

    113. 7/31/2001 WLT Extracting a Verilog Netlist Back in the Verilog-XL Integration window, click on Simulation -> Start Interactive. The first time you run the verilog netlist extraction, you will get two errors regarding inherited nets for every instance you have in your design (on the order of a few thousand errors for our design). Ignore these errors - they are internal errors and should be fixed in the latest version of ICFB. Click on Simulation -> Start Interactive again; you will not get these errors the second time.

    114. 7/31/2001 WLT Extracting a Verilog Netlist 20. Ignore the warning shown below (click on OK). We can ignore this warning because we are not going to run Verilog simulation in ICFB.

    115. 7/31/2001 WLT Extracting a Verilog Netlist 21. A text file called verilog.inpfiles, located in the netlister work directory (cadence/icfb/topchip_nopads.verilog) is created. This file tells of the location of the Verilog netlists generated. 22. Using a text editor (pico, VI etc.), view the file verilog.inpfiles. 23. The text file will tell you the location of the top-level Verilog netlist – it is going to be in ihnl/cds?/netlist, where ‘?’ will be a number.

    116. 7/31/2001 WLT Extracting a Verilog Netlist 24. Copy the netlist file from cadence/dfII/topchip_nopads.verilog/ihnl/cds?, to cadence/dfII/gate. In the directory /cadence/dfII/gate, rename the netlist file to topchip_nopads_icfb.v. Use a text editor to view your verilog netlist. If the top-level module of topchip_nopads_se.v is not topchip_nopads, edit it to that name. 27. The next section of this tutorial will demonstrate how to simulate this Verilog netlist using Modelsim. However, before we go into that, let’s discuss some other issues regarding ICFB.

    117. 7/31/2001 WLT Extracting a Hspice Netlist The procedure for extracting a Hspice netlist is similar to that of extracting a Verilog netlist, up to the Extractor form. There is only one difference for the Extractor form: In the Extractor form, select Flat for Extract Method instead of Macro Cell.

    118. 7/31/2001 WLT Extracting a Hspice Netlist After running the Extractor form, follow the instructions below to generate a HSPICE netlist: Click on Tools -> Simulation -> Other. You should see a new menu item - Simulation – appear on your menu bar. 2. Click on Simulation -> Initialize. 3. Enter “topchip_nopads.hspice” for the simulation run directory. 4. Click on OK. 5. Another Initialize Environment form should pop-up. This one has the full set of options to choose from.

    119. 7/31/2001 WLT Extracting a Hspice Netlist In the Initialize Environment form, choose hspice for the simulator name. Enter “Tutorial” for Library Name, “topchip_nopads” for Cell Name, and “extracted” for View Name.

    120. 7/31/2001 WLT Figure 29: Initialize Environment Form

    121. 7/31/2001 WLT Extracting a Hspice Netlist Go back to the Layout editing window, and click on Simulation -> Options… Make sure the Use Hierarchical Netlister and Re-netlist Entire Design boxes are checked, and the others are left unchecked.

    122. 7/31/2001 WLT Extracting a Hspice Netlist Go back to the Layout editing window, and click on Simulation -> Netlist/Simulate… Make sure that the netlist box is checked, and the simulate box is not. Also, check the Run in background box. The remaining information should be already filled in correctly for you. Make sure they match up to that shown in Figure 30. (next slide)

    123. 7/31/2001 WLT Figure 30: Netlist and Simulate Form

    124. 7/31/2001 WLT Extracting a Hspice Netlist Click on OK. Wait for a minute or so as ICFB works in the background to generate the Verilog netlist. A message telling you that the netlister has succeeded should pop up after a minute or so. The HSPICE netlist will be located in the directory that you specified as the run directory (for our case, cadence/dfII/topchip_nopads.hspice), with the filename netlist.

    125. 7/31/2001 WLT Verilog or Hspice? For our case, Verilog is a more practical choice. Verilog is a switch-level language, which means it does not model any parasitics of the design. This makes simulation much faster than Hspice, which models the parasitics of the system. Since we started out with a VHDL file, we can assume that most of our designs will be relatively complex (e.g. having more than a few thousand transistors). Hspice simulation for designs of this scale is too time consuming.

    126. 7/31/2001 WLT Verilog or Hspice? For example, if we were to simulate our topchip_nopads design using Hspice for 150 us, it would take more than 24 hours to simulate. Verilog simulation using Modelsim takes less than 1 second. Conclusion: Hspice is great for detailed simulations (especially for analog systems), but for complex, purely digital systems, Verilog simulation is much more practical. Other simulators such as IRSim fall somewhere in between Verilog and Hspice simulators.

    127. 7/31/2001 WLT DRC Verification (ICFB) DRC (Design Rule Check) verification checks for design rule violations. The NCSU Cadence Design Kit comes with a decent (but by no means perfect) DRC checker. The NCSU kit DRC checker will flag certain metal constructs that should not be flagged as errors. Refer to the next slide for a more detailed explanation.

    128. 7/31/2001 WLT DRC Verification (ICFB) The NCSU kit DRC checker will flag these as errors if the spacing is less than the minimum spacing for that metal layer, even though it should not matter because they all belong to the same net.

    129. 7/31/2001 WLT DRC Verification (ICFB) Open the topchip_nopads layout using the layout editor. Click on Verify -> DRC… Check Flat for checking method, and Full for checking limit. Click OK. DRC will run (this will take a few minutes), and subsequently return around a thousand false metal spacing errors.

    130. 7/31/2001 WLT Figure 31: DRC Form

    131. 7/31/2001 WLT Checking for Short Circuits between VDD and GND The easiest way to make your layout fail, is to have accidental shorts between VDD and GND. Shorts between VDD and GND can easily occur during manual layout procedures (e.g. when connecting the VDD and GND pads to the supply rings). Verilog extraction will not detect shorts between VDD and GND, because our Verilog simulating method ignores the VDD and GND nets. Therefore, it is essential to perform a quick check to make sure VDD and GND are not shorted.

    132. 7/31/2001 WLT Checking for Short Circuits between VDD and GND A simple way to perform this check is to open the extracted view of the layout. In the Library Manager window, open with extracted view of topchip_nopads. Now, click on the VDD (or GND) ring. If you clicked on the VDD ring, you should see the VDD ring, and the VDD rails highlighted. The same goes for the GND ring. If you see both rings highlighted when you click on either ring, then a there is a short from VDD to GND in your layout that must be fixed.

    133. 7/31/2001 WLT Exporting to CIF Most industrial foundries use a standard design transfer file format to send or receive design files. CIF is one such format. To export to CIF, click on File -> Export -> CIF… Enter ‘.’ for the run directory, “tutorial” for the library name, “topchip_nopads” for the cell name, and “layout” for the view name.

    134. 7/31/2001 WLT Exporting to CIF Enter “cif_files/topchip_nopads.cif” for the output file. Check the CIF DB box. Click on OK. This will generate a CIF file called topchip_nopads.cif in the cadence/dfII/cif_files directory. You will get some warnings (view the PIPO.LOG file) because not all layers in ICFB are translated into the CIF file. This is OK.

    135. 7/31/2001 WLT Figure 32: CIF Out Form

    136. 7/31/2001 WLT Modelsim The final step in our design flow is to simulate our ICFB-generated Verilog netlist using Modelsim. If the place-and-route procedures were successful, we should get the same results for this simulation as the simulation we ran with our Synopsys-generated Verilog netlist.

    137. 7/31/2001 WLT Modelsim There should be the following Verilog files in the cadence/dfII/gate directory: topchip_nopads_icfb.v, which we just created, tb_topchip_nopads_icfb.v, the testbench file for the file above.

    138. 7/31/2001 WLT Modelsim Change to the qhsim directory. Type swsetup modelsim. 3. Type qvlcom ../cadence/dfII/gate/libcells_icfb.v 4. Type qvlcom ../cadence/dfII/gate/topchip_nopads_icfb.v 5. Type qvlcom ../cadence/dfII/gate/tb_topchip_nopads_icfb.v

    139. 7/31/2001 WLT Modelsim Type qhsim tb_topchip_nopads &. This will invoke Qhsim to simulate the testbench. There is a .do file in the qhsim directory that displays the signals and wave windows, adds all the top level signals into the wave window, and runs the simulation for 150 us. Activate the script by typing “do tb_topchip_nopads.do” in the command window. If you open up that .do file you will find that it contains the same commands that you would type in the command window to achieve the same results.

    140. 7/31/2001 WLT Modelsim Verify that the results for this simulation match that of the first Verilog simulation in this tutorial, by looking at the wave window.

    141. 7/31/2001 WLT Figure 33: Simulation Results Waveform

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