1 / 14

EE311: Junior EE Lab 555 Timer

EE311: Junior EE Lab 555 Timer. J. Carroll 8/26/03. Background. The 555 timer can operate as a monostable multivibrator, i.e., a ``one-shot’ an astable multivibrator, i.e., an oscillator behavior dependent on external R, C values Various analog and digital applications

emily
Download Presentation

EE311: Junior EE Lab 555 Timer

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. EE311: Junior EE Lab555 Timer J. Carroll 8/26/03

  2. Background • The 555 timer can operate as • a monostable multivibrator, i.e., a ``one-shot’ • an astable multivibrator, i.e., an oscillator • behavior dependent on external R, C values • Various analog and digital applications • voltage ramp generator, missing pulse detector, pulse width modulator • power supply in the range of 5-18 volts • with 5-volt supply, compatible with TTL or CMOS digital devices

  3. Background • 555 timer IC • a SR latch • two analog comparators • an totem pole output stage • a discharge transistor • a voltage divider network

  4. Set-Reset (SR) Latch Operation • SR latch has has two stable states • State 1  latch is set, i.e., Q=1,~Q=0 • State 2  latch=reset, i.e., Q=0,~Q=1 • note: circuit can remain in (hold) either state • Trigger pulses can be applied to either S or R inputs to change the latch state • S=1 (high) “sets” the latch , i.e., Q=1 (high) • R=1 (high) “resets” the latch , i.e., Q=0 (low) • note: the first input to go high has priority • Timer output tracks Q  output high when Q=1

  5. Role of the Analog Comparators • A comparator compares two input voltages and determines which is larger • if V+>V-, the comparator output is high or “1” • if V->=V+, the comparator output is low or “0” • The 555 timer uses two comparators to generate the S and R inputs to the latch • a voltage divider network of three equal valued resistors is used to generate V+=Vcc/3for COMP1 and V-=2Vcc/3for COMP2 • COMP2 compares the THRESHOLD to 2Vcc/3 • COMP1 compares the TRIGGER to Vcc/3

  6. Role of the Analog Comparators • A comparator compares two input voltages and determines which is larger • if V+>V-, the comparator output is high or “1” • if V->=V+, the comparator output is low or “0” • The 555 Timer uses two comparators to generate S (COMP1) and R (COMP2) inputs to the latch • a voltage divider network of three equal valued resistors is used to generate V+=Vcc/3for COMP1 and V-=2Vcc/3for COMP2 • COMP1 compares the TRIGGER (Pin 2) to Vcc/3 • COMP2 compares the THRESHOLD (Pin 6) to 2Vcc/3

  7. Role of the Discharge Transistor • A discharge transistor is used to clamp an external capacitor (Pin 7) to ground • the transistor is ON (conducting) when ~Q=1, discharging the capacitor at a rate determined by the associated time constant, i.e., R and C • when ~Q=0 the transistor is OFF (open) leaving the capacitor unclamped, i.e., holding its voltage

  8. Monostable (One-shot) Circuit • At power up • latch is reset, Q=0,~Q=1 • output is LOW • Pin 2 goes LOW • latch is set,Q=1,~Q=0 • output goes high • Cx charges to Vcc, with t=RxCx • Pin 6 goes HIGH • latch is reset,Q=0,~Q=1 • output goes LOW, PW=1.1 RxCx

  9. Astable (Oscillator) Circuit • Two quasi stable states are possible • latch is set,Q=1,~Q=0  PW1=0.695(RA+RB)CX • latch is reset, Q=0,~Q=1  PW2=0.695RBCX • output frequency f = 1/(PW1+PW2) = 1.439/((RA+2RB)CX) • waveform duty cycle D = PW1 /(PW1+PW2) = (RA+RB)/(RA+2RB)

  10. Preliminary Lab Questions 1. Lookup up and record the physical location of the pins on the 555 timer chip 2. The 555 timer is designed so that the timing characteristics, e.g., frequency, pulse width and duty cycle, are independent of the power supply voltage • justify this statement theoretically, e.g., using circuit analysis, etc.

  11. Preliminary Lab Questions 3. Experiment with the demo VI's associated with the LabVIEW 555_Monostable.llb library • based on these applications, describe in detail how a 555 timer IC could be used to create an inexpensive meter to measure an unknown capacitance in the range 0.001 to 1000uF 4. For step 1 of the Procedure, calculate the expected time that the LED will remain lit after the switch is released when pin 4 is connected to Vcc

  12. Preliminary Lab Questions 5. Experiment with the demo VI's associated with the LabVIEW 555_Astable.llb library • observe the timer output waveform and duty cycle when RA>RB, RA=RB, and RA<RB • based on these applications, describe in detail how a 555 timer and a thermistor could be used to create an inexpensive temperature transducer 6. For step 2 of the Procedure, calculate the expected frequency and duty cycle of the output at pin 3

  13. Preliminary Lab Questions 7. For step 3 of the Procedure, use PSpice to show the expected waveforms at pins 2 and 3 of the 555 timer chip when Vcc=12V • determine the frequency, duty cycle and the amplitude of the output at pin 3 • repeat the above with Vcc=6V

  14. Discussion of the Lab Procedures • Bonus points will be awarded on the lab report to those groups that implement and document the required lab measurements using LabVIEW

More Related